Hi,
Our design involves a DAC3482, with digital samples being supplied at 480MHz DDR by an FPGA (DATA_CLK = 480MHz) and DAC_CLK at 960MHz. Hence an interpolation factor of 2 is chosen. Power-on sequence was followed as per the datasheet. Timing constraints have been taken care at FPGA end. Following are the register settings applied at the DAC :
config1 : 0x050E
config16 : 0x3000
config5 : 0x0000 (Cleared alarms)
config27 : 0x0800
config32 : 0x2201 (Single Sync source mode with Frame being used at the sync signal)
config0 : 0x019C (Interpolation set to 2x)
config9 : 0x8000
config2 : 0xF002 (Word-wide mode, 2's compliment format)
config7 : 0x4063 (Only alarm from PLL is masked, others are enabled/unmasked)
config36 : 0x0000 (data_dly and clk_dly are made 0, since this is taken care of at FPGA end, by centre-aligning the data with respect to data_clk)
config5 : 0x0000 ( To clear alarms after power-on sequence)
After following this sequence, a register read of config5 shows no collision alarm (config5 : either of 0x0060, 0x0860 or 0x1860).
But after supplying the samples from FPGA, a collision occurs (config5: 0x3960), which after clearing once goes back to 0x0060 (no collision). There is no report of collision then onwards.
Any help in debugging this issue would be much appreciated.
Note: Same experiment carried out with DATA_CLK = 240MHz and DAC_CLK = 960MHz with 8x interpolation caused no issues such as the above mentioned one.
Regards,
Shishir