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ADC12J4000: ADC12J4000

Part Number: ADC12J4000


We use an ADC12J4000 with a periodic SYSREF (about 2.56??Mhz) strictly synchronous with DEVCLK (about 4Ghz) through using a device similar LMK048??.

The periodic SYSREF is a clock with 50% duty-cycle. We can't change the duty-cycle.The number of periods DEVCLK is bigger than the number min of 8 periods DEVCLK in the datasheet during  a state '1' of SYSREF  .

The SYSREF is a sub-harmonic of the LMFC internal timing.

In the SYSREF Capture Control and Status, the SYSREF Capture is OK (no dirty)

What happen to the synchronism between SYSREF and LMFC? Can ADC12J4000 lose this synchronism because during a state '1' SYSREF , this one is captured on a  rising edge DEVCLK and during the following state '1' SYSREF, this one is captured on another rising edge DEVCLK ? can ADC12J4000 never to receive a signal SYNC from FPGA, receiver of lanes JESD ?

Thank tou

  • Hi Antoine

    Your described system should work just fine.

    The SYSREF detection circuitry inside the ADC12J4000 responds to the rising edge event on SYSREF. The event that is captured is a low SYSREF on the previous rising edge of DEVCLK and a high SYSREF on the next rising edge of DEVCLK. Holding SYSREF high for additional DEVCLK edges is OK and doesn't cause additional SYSREF detections to occur. Please refer to Figure 2 in the ADC12J4000 datasheet.

    For another valid SYSREF detection to occur, SYSREF must first be low t(PL-SYS) and then transition high again.

    Best regards,

    Jim B