DAC38J84EVM: J25 - LMK SPI

Apparently there's a way to do this with the SPI_SELECTOR (JP3), which is not mentioned anywhere in the user's guide.

If someone from TI could send me more information I'd appreciate it.

Is anybody there? I'm trying to use the LMK04828's on the TI DAC37J84EVM to do JESD204B Subclass 1 - I don't see any reference to how we can control the LMK, I'm not sure what the CPLD is doing.

Travis,

By default, when using the GUI quick start tab, the DAC is programmed for subclass 1 mode. If you want to change settings of the LMK, there is a LMK04828 tab at the top level of the GUI that contains sub tabs to allow you to change the LMK settings.

The default configuration for this The CPLD source code, by default, sends the commands from the FTDI chip to both the LMK and the J25 for monitoring. If you want to write to the LMK using J25, you will have to modify the source code for U1. The source code is attached.

Can you send me exactly what you are trying to do and I will generate a configuration file that will load both the DAC and LMK with the required settings. 

Regards,

Jim

 

Hi Jim,

I don't see an attached source.

I have two DAC37J84EVM boards attached to a hi-tech global HTG-K800 - trying to synchronize the dual LMK04828's on the two boards for JESD204B Subclass 1, then exercise both DACS and show they're aligned.

The DAC37J84 EVM boards have both been modified so the OSCIN path is usable:

The overall clocking plan is this:

We're trying to use the OSCIN path for lowest phase noise in single loop 0-delay mode, per the draft app note from Tim Toroni @ TI, so PLL1 can be shutdown (we're only using PLL2). I've verified the input 20MHz clock, but I don't see anything coming out (I am in the process of checking jumpers/tracing signals/checking input SPI/etc, but I wanted to send this reply ASAP).

This LMK usage on the DAC37J84EVM most closely resembles "Clock Generator using External Reference" (slau547b, page 15). If you have any thoughts so far, I'd greatly appreciate it!

Travis,

The LMK uses the clock from pins CLKIN1 when the GUI selects external clock source, so this will not work with your setup. When we did a similar demo ourselves, we used the setup with two LMK's as shown in the attached file, which works with the GUI as this uses the CLKIN1 pins. Using this mode required no modification to the EVM's and provides what we believe is the best method to synchronize two LMK devices. The CPLD code is attached as well.

Regards,

Jim

Dual LMK04828 CLOCKING SETUP.pptx6747.DAC38J84_CPLD.v

Travis,

Follow the instructions in the attached file with your current setup and see if you can get the PLL2 to lock. You must get this to occur to get a valid clock out of the LMK. This example will provide a 740MHz clock to the DAC. What is you target frequency? What interpolation do you plan on using? The phase noise of the LMK will increase with a lower reference clock. Why are you using 20MHz?

Regards,

Jim

DAC38J84_EXT_OSC_IN_20M.pptx 

Are you sure the first GUI page should be 'use onboard clock' - we popped it off to make way for an SMA connector to get to get access to OSCIN with 20MHz, but it looks like OSCIN should be available to PLL2 without any register settings.

Anyway, I tried these settings with 2 DAC37J84EVM boards, and could not get PLL2 to lock; a colleague tried independently with the same results.

Is there anything else we can try?