Other Parts Discussed in Thread: LMX2582, LMK04828,
Dear sir,
We are using 2 nos of ADC12DJ3200 for our requirement where multiple ADC synchronization is required.
Stage 1 :
Operating the two ADC's at device clock of 3.2GHz in which maximum SYSREF frequency of 10MHz as per equation 2 in datasheet.
Which is able to generate from LMK04828B PLL and Device clock of 3.2GHz from LMX2582 RF PLL.
Stage 2 :
If device clock of 1.35GHz and require SYSREF frequency to be 4.21875MHz (max)
But we are unable to generate these frequency from LMK04828.
These are frequency & divider settings for SYSREF in LMK04828 PLL.
VCO Frequency : 3000MHz
SYSREF Divider Value : 711
SYSREF output Frequency : 4.219409MHz
There is frequency offset of 65.9KHz.
Query :
1. Whether these frequency offset is acceptable for multiple ADC synchronization.
2. What will be impact of synchronization over temperature range with this frequency offset.
Regards,
Jaya Bharath Reddy K