• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 46 subscribers
  • Views 611 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TVP700x Settings for RGB 4:4:4 Conversion with Sync on Green (SOG)?

Bernie Thompson TI
Mastermind 41665 points
Other Parts Discussed in Thread: TVP7001, TVP7002

I am looking for some settings for a TVP7001 application where it needs to convert to RGB 4:4:4 from a camera providing:

-Analog RGB
-Interlaced
-Sync on green
-768x494 resolution

Does anyone know of any example register settings that could be used to start with to get to this configuration (or that happen to have this kind of configuration)?

I have come across TVP7002 EVM settings that capture YCbCr 4:2:2 with SOG(Y), so I am wondering if one can just set it to 4:4:4 in place of 4:2:2 and adjust the resolution or if there are other significant changes to be made?

  • 0
    TI__Genius 16810 points

    Bernie,

    Try the settings below for this format.  It is not clear what the total pixels per line are for this format.  The settings below are based on a camera found that specified 768 active and 811 total pixels/line.  This may requrie adjustment for your camera.  A 2x PLL setup with DIV/2 was used to improve jitter performance.

    The TVP7002 is recommended over the TVP7001 for improved performance.

     

    ////////////////////////////////////////////////////////////////////////////////
    //This setup uses a 2x H-PLL setup to improve clock jitter at low frequencies
    //H-PLL DIV must be adjusted to conform to the camera total pixels per line
    //Bottom level clamping is selected to support RGB inputs.
    //MUX settings may require change to match actual H/W
    ////////////////////////////////////////////////////////////////////////////////

    BEGIN_DATASET  // Appended by WinVCC4 v4.52.  Saved all registers.

    DATASET_NAME,"TVP7000_768(H)x494(V) active_811(H)x508(V) total -  2x PLL DIV2 "

    //TVP7000
    WR_REG,TVP7000,0x01,0x01,0x65 // H-PLL DIVMSB    811x2 = 1622           
    WR_REG,TVP7000,0x01,0x02,0x60 // H-PLL DIVLSB                 
    WR_REG,TVP7000,0x01,0x03,0x10 // H-PLL CONTROL                
    WR_REG,TVP7000,0x01,0x04,0x81 // PHASE SEL(5) DIV by 2  1622/2 =811 total pixels pe line
    WR_REG,TVP7000,0x01,0x05,0x06 // CLAMP START                
    WR_REG,TVP7000,0x01,0x06,0x10 // CLAMP WIDTH
    WR_REG,TVP7000,0x01,0x07,0x40 // HSYNC OUTPUT WIDTH - 64
    WR_REG,TVP7000,0x01,0x08,0x3C //Blue Fine Gain
    WR_REG,TVP7000,0x01,0x09,0x3C //Green Fine Gain
    WR_REG,TVP7000,0x01,0x0A,0x3C //Red Fine Gain

    WR_REG,TVP7000,0x01,0x0E,0x24 // SYNC CONTROL    HSout+ VSout+
    WR_REG,TVP7000,0x01,0x0F,0x2E // PLL and CLAMP CONTROL
    WR_REG,TVP7000,0x01,0x10,0x58 // SOG Threshold-(Bottom level clamping for RGB)   
    WR_REG,TVP7000,0x01,0x11,0x40 // SYNC SEPERATOR THRESHOLD   
    WR_REG,TVP7000,0x01,0x12,0x03 // PRE_COAST                  
    WR_REG,TVP7000,0x01,0x13,0x03 // POST_COAST
    WR_REG,TVP7000,0x01,0x15,0x04 // Output Formatter
                 
    WR_REG,TVP7000,0x01,0x17,0x00 // MISC Control 2  Enable Outputs, FID out
    WR_REG,TVP7000,0x01,0x18,0x01 // MISC Control 3 Clock polarity
                    
    WR_REG,TVP7000,0x01,0x19,0x00 // INPUT MUX SELECT    CH1 selected (BNC )      
    WR_REG,TVP7000,0x01,0x1A,0x17 // INPUT MUX SELECT2,  SOG and Clamp filter, internal REFCLK selected
    WR_REG,TVP7000,0x01,0x21,0x0C // HSOUT START
    WR_REG,TVP7000,0x01,0x22,0x08 // MACEN

    WR_REG,TVP7000,0x01,0x26,0x80 // ALC Enable     
    WR_REG,TVP7000,0x01,0x28,0x53 // Default ALC FILTER Control          
    WR_REG,TVP7000,0x01,0x2A,0x87 // Enable FINE CLAMP CONTROL
    WR_REG,TVP7000,0x01,0x2B,0x00 // POWER CONTROL-SOG ON
    WR_REG,TVP7000,0x01,0x2C,0x50 // ADC Setup
    WR_REG,TVP7000,0x01,0x2D,0x00 // Coarse Clamp OFF
    WR_REG,TVP7000,0x01,0x2E,0x80 // SOG Clamp ON
    WR_REG,TVP7000,0x01,0x31,0x18 // ALC PLACEMENT
    WR_REG,TVP7000,0x01,0x34,0x24 // Macrovision Stripper Width - use 24h when the internal REFCLK is used
    //WR_REG,TVP7000,0x01,0x34,0x83 // Macrovision Stripper Width - use 83h when the exteraml 27MHz REFCLK is used
    WR_REG,TVP7000,0x01,0x35,0x00 // VSout Align
    WR_REG,TVP7000,0x01,0x36,0x00 // Sync Bypass
    WR_REG,TVP7000,0x01,0x3D,0x06 // Line Length Tolerance (Pixel Tolerance)
    WR_REG,TVP7000,0x01,0x3F,0x0F //Video B/W control

     

    END_DATASET

    ////////////////////////////////////////////////////////////////////////////////

  • 0 in reply to Larry Taylor
    TI__Mastermind 41665 points

    Thanks for the fast response, this sounds like it is just what I was looking for.