ADS52J90: Question of JESD_RESET1

masahiko shimizu

Part Number: ADS52J90

Hi,

Could you answer below questions about JESD_RESET1, please?
JESD_RESET1 is showed in datasheet page of 57~

Q1: What does ADS52J90 do the reset of JESD Block?
->Only reset of LMFC clock divider? or All reset of JESD Serial Interface Registers?

Q2: What is "SYSREF event"?
->Is it every rise edge of SYSREF clock? or Is it only SYSREF clock edge of mismatch timing?

Best regards,
Shimizu

over 7 years ago

0 Olu Sodipe over 7 years ago

TI__Expert 4145 points

Hi Shimizu-san,

We have received your inquiry and will get back to you next week.

Sincerely,

Olu

0 masahiko shimizu over 7 years ago in reply to Olu Sodipe

Guru 11235 points

Hi Olu-san,

How is the progress about this?

Best regards,
Shimizu

0 Olu Sodipe over 7 years ago in reply to masahiko shimizu

TI__Expert 4145 points

Hi Shimizu-san,

The JESD TX block as specified in Figure 72 contains the transport, link and physical layers. The subsequent pages in the datasheet go over what each layer contains. The JESD serial interface registers are used to configure the JESD TX block and are not reset on JESD_RESET1.

Figure 75 on Page 59 of the datasheet shows what a SYSREF event looks like with the SYSREF assertion (active high) not latched into the device until the next input ADC clock rising edge.

Sincerely,
Olu

0 masahiko shimizu over 7 years ago in reply to Olu Sodipe

Guru 11235 points

Hi Olu-san,

Thank you for your reply.
My understanding has deepened.

When SYSREF which is clock pulse (not one-shot) is used, Should we mask the JESD BLOCK reset by JESD_RESET2 register?

Best regards,
Shimizu

0 Olu Sodipe over 7 years ago in reply to masahiko shimizu

TI__Expert 4145 points

Hi Shimizu-san,

For a continuous SYSREF signal, JESD_RESET1 is probably the way to go so the SYSREF signal always resets the JESD block on assertion while not affecting the other portions of the ADC.

Sincerely,

Olu

0 masahiko shimizu over 7 years ago in reply to Olu Sodipe

Guru 11235 points

Hi Olu-san,

Thank you for your reply.

Is your answer of below "Yes"?

>When SYSREF which is clock pulse (not one-shot) is used, Should we mask the JESD BLOCK reset by JESD_RESET2 register?

Best regards,
Shimizu

0 Olu Sodipe over 7 years ago in reply to masahiko shimizu

TI__Expert 4145 points

Hi Shimizu-san,

Not necessarily. JESD_RESET2 prevents SYSREF from resetting any portion of the device. It's used to prevent accidental reset of the JESD block and other parts of the device after SYSREF has already been used to reset the LMFC.
I'll still recommend JESD_RESET1 even for a pulsed SYSREF. You can also assert JESD_RESET3 to make sure only the first SYSREF signal resets the LMFC and subsequent ones do not.

Sincerely,
Olu

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ADS52J90: Question of JESD_RESET1