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ADC3444: Issue with clock input

Brandon Heavey
Prodigy 20 points
Part Number: ADC3444

I'm using the ADC3444 in a design.  I modeled my clk input circuitry after figure 149 in the datasheet which is a single-ended, ac-coupled cmos input driving the clkp pin and the clkn pin connected to ground via a 0.1uF cap.  When probing on a scope, I see the clk input signal at clkp, but I'm not seeing any output on the frame clk leading me to believe there is some issue with my clk input.  I double checked the pdn pin and it's pulled low.  Has anyone successfully used a singled ended, ac coupled cmos clk to drive this part?  Or does anyone have a suggestion on why I wouldn't be seeing the frame clk output?

Thanks.

  • 0
    TI__Genius 12780 points
    Hi Brandon,

    We are looking into it, and will get back with you soon.

    Regards,

    Dan
  • 0
    TI__Intellectual 785 points
    Hi Brandon,
    Can you please share schematic of your design? Device should be able to work with single-ended sampling clock. Do you see a change in power consumption by device when you switch off the sampling clock? What is the sampling frequency?
    Please also share the register writes you are using to program the device.
    Regards,
    Sourabh
  • 0 in reply to Sourabh Gupta
    Prodigy 20 points

    Thank you for the follow up.  It turns out, I may have been fooling myself.  Yesterday I uncovered that the assembly house that populated my board did a very poor job attaching the ADC and not all the pins are making good contact.

    Let me deal with this issue first and see if it resolves my clock problem.  If not, I'll reply to this message and get back to you.  Thank you for your time.