TSW40RF80EVM: Request Configuration File

Hi,

We'll work on this config file and expect to send it by mid-next week.

Regards,

satish.

Louis,

I need some clarification on the configuration you asked for. They're:

1. What is the DAC sampling clock frequency? In your requirements, you had stated DAC Clock (LMK's DCLKout2) to be 2949.12M. Is this going to be the reference frequency for the DAC PLL? If so, it can't be this high. Or do you want to clock the DAC at this rate?

2. Are the interpoaltion and decimation both 16?

3. When I setup the HSDC Pro with the LMFS, interpolation and (assumed) DAC sampling clock of 2949.12M, I get the FPGA clock as 92.16M, not 184.32M you have stated.

So, please check the parameters and let me know.

Regards,

satish.

Hi Satish

1. What is the DAC sampling clock frequency? In your requirements, you had stated DAC Clock (LMK's DCLKout2) to be 2949.12M. Is this going to be the reference frequency for the DAC PLL? If so, it can't be this high. Or do you want to clock the DAC at this rate?

DAC Sampling rate : 2949.12Mhz

2. Are the interpolation and decimation both 16?

interpolation : 16

decimation  : 16

3. When I setup the HSDC Pro with the LMFS, interpolation and (assumed) DAC sampling clock of 2949.12M, I get the FPGA clock as 92.16M, not 184.32M you have stated.

Don't care.

Please Can you respond quickly?

regards.

Louis,

I have emailed the configuration file and the instruction to you and Sam. It setups the ADC. I'm working on the DAC configuration and will send once I verify it's functionality.

Regards,

satish.

Hi Satish

I was receive email well.

Thanks for your support.

when do you send to me DAC configuration file?

regards.