Other Parts Discussed in Thread: ADC32RF44
According to the ADC32RF45 datasheet, when an ADC channel has decimation enabled, I should be able to enable a few different data test patterns that replace the ADC samples. This is described (inconsistently) in two places:
- In section 8.3.10.1, the Test Pattern Options register is described to be at offset 0x37 from the decimation filter page (so address 0x5037 for channel A and 0x5837 for channel B). Here it says that bits 7-4 control the test pattern output, with the default 0000 corresponding to actual ADC output samples.
- In section 8.5.12.22, there is a similar description, only it says that bits 3-0 of the register at offset 0x37 control the test pattern. It says that the other bits must be written with zeros.
Which of these descriptions (if any) are correct? In my application, I'm streaming samples from channel A's DDC with a decimation factor of 4. I've tried applying the different test pattern settings to the specified register, but I never see any test patterns, only the actual ADC sample data. Since the datasheet gives two descriptions of where the bits are, I've tried both. For example, in order to try to enable the digital ramp test pattern, I've written the following values:
register 0x5037 = 0x04
and
register 0x5037 = 0x40
Neither had any effect on the data stream. The only other register settings that are related to the test pattern are in register offset 0x3A, TEST PAT RES and TP RES EN. These are described to "reset" the test pattern. The description is pretty terse, but I've tried manipulating these bits in every way I can think of and still have not seen an effect on the data stream.
Are these test modes functional in production models of the ADC32RF45? I noticed that the ADC32RF44 has some additional fields and registers documented in its datasheet, but I didn't see anything substantive that differed from the ADC32RF45 (and I"m not sure it would apply anyway).
