ADS5407: ADC SYNC & SYNCOUT

Zhoulc,

How many of these repeaters are you using? Are you sending them all a single pulse or a 32 clock cycle signal per the ADC data sheet? Are any of the 64 converters synchronized? How fast are you sampling at? Is there a chance there is a timing issue with the Xilinx device?

Regards,

Jim 

Hi, Jim,
I attempt to test synchronization with 2 ads5407 and a fpga, and in my project, sample clk is 500MHz, so i have the fpga to produce a periodic pulse (15.625M) for sync input. All 2 sync signal is distributed by a buffer with low skew, and layout in PCB is at the same length. Moreover, two format sync signal, both periodic pulse sync and one time pulse sync, are all tested, and there is no improvement.

Zhoul,

Can you send a screen shot of the outputs, CLK and SYNC_IN for the two parts? How many clock cycles are they off? Does this amount change from input SYNC to input SYNC rising edge? Have you tried just using a single SYNC pulse?

Regards,

Jim

figure 1 shows sync signal at ads5407 SYNC pin. As i said before, it's a 15.625MHz periodic pulse which repeat every 32 CLKIN(500MHz) cycles.

figure 2 is chipscope view window,  red signal is the sync signal produced from fpga and the signal on board is just as figure 1. But sync_ref signals which get from syncout pins are not stable and periodic. I have tried one-time pulse but i had the same result.