This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1243 offset null problem

Other Parts Discussed in Thread: ADS1243

I am using the ADS1243 in an half bridge measurement application where the ADC reference is derived from the bridge excitation voltage Vexc, and the ADC is intended to measure sensor output ideally spanning from 0 to Vexc against an half-way voltage point obtained from the same bridge excitation voltage Vexc by using a precision resistive divider (sketch attached, %Vsupply, up to 5V Vref, RANGE=1).

The system is intended to measure voltages in the 0.5Vexc to Vexc range doubling the ADC native Vref/2 range with a "software trick": sensor voltages in the (0.5 Vexc to Vexc) range are measured connecting the sensor output to the ADC positive input and the half-way voltage point (= 0.5 Vexc) to the ADC negative input, while sensor voltages in the (0 to Vexc) range are measured inverting the inputs, that is connecting the sensor output to the ADC negative input and the half-way voltage point (= 0.5 Vexc) to the ADC positive input. The software do the work of inverting positive and negative inputs when zero ADC output is read, taking a new ADC read after the input inversion and then multiplying the new non-zero ADC output by -1 so that code -16777216 is obtained for 0V sensor output and code  +16777216 is obtained for Vexc sensor output. The disadvantage of the trick is that a real "zero" ADC output code cannot be read, however since several (10...16) successive readings are averaged to produce the final trusted sensor reading the interval of missing codes around the "zero" is pushed reasonably low (close to twice the noise level in my evaluation).

In the real world things works very well when the sensor output moves inside the same (0 to 0.5 Vexc) or (0.5 Vexc to Vexc) interval but, when it crosses the boundary at 0.5 Vexc an unexpected shift apperas: for example at sensor output inside the (0.5 Vexc to Vexc) range I have ADC readings between 5958 and 5664 (noise around 300 = 45uV), moving down I have readings between 2312 and 1975 (50uV noise) and finally when I get close enough to the boundary (reding below 300..350) to activate the software trick that inverts the ADC inputs due to the noise, I experience readings between codes 38 and -4044 (that would be 610uV noise). The strange thing is that when I move deeper into the new (0 to 0.5 Vexc) interval I have again a lower noise, for example readings between -6929 and -7252 (noise 323 = 48uV).

It seems like an anomalous offset shift of amplitude around 3782 ADC code appears just due to the inversion of the inputs.

Device self offset and gain calibration is performed each time a reading cycle is started following this procedure:

- device reset,

- clear setup register to force gain = 1 and Burnout = off

- write to ACR register to isable input buffer and clear the RANGE bit

- clear ODAC

- self gain calibration

- self offset calibration

- write ACR for normal operations

- dummy ADC read to purge buffer

I did an additional test to see where this offset comes from, since I supposed that after ADC calibration, connecting both positive and negative ADC inputs to the same pin (same mux setting for pos and neg input) the ADC should read close to zero, but I was suprised to see that setting the MUX register to connect both ADC inputs to the half-way voltage point pin the ADC reading was between 2013 and 1873, while conneting them both to the sensor output I had ADC readings between 1959 and 1838

Curiously this unexpected boundary crossing "offset" is very close to the sum of the two unexpected offsets measured with both adc inputs routed on the same pin.

Is there an explanation for this?

How can I get rid of this "extra" offset?

Thanks in advance

 

  • Hi fbj,

    Thanks for the very detailed problem definition!  I've never seen this boundary crossing error, so off the top of my head I can't give you an explanation - we'll try to run the part in a manor similar to what you describe in order to replicate your setup.  Will let you know what we see on our side and give you feedback as soon as possible. 

  • fbj,

    Here are a couple of things to note.  The ADS1243 SELFCAL only calibrates the internal portion of the ADC.  I think what you are seeing is offset due to the mux.  If you do a SYSCAL, you should be able to reduce the offset error.  You can also use the offset DAC to shift the input, but I don't think that will really be of much help in this situation.  Also, keep in mind that there is some current that flows into the inputs, which means there will be a small voltage drop across the 100 ohm resistor.  With the buffer off, the impedance is 5M ohm.  It doesn't seem like much, but at the 24-bit level it can shift the swing considerably by 10s to 100s of uV.  I know you won't get the same resolution, but you might try using the buffer to see the results at the same boundary point.  The buffer is chopper stabilized and the input impedance jumps to 5G ohms.

    Best regards,

    Bob B

  • First of all that you for your prompt reply.

    This is something that makes a man with a problem to feel less alone in the world ;-)

    From the moment I found that the magnitude of the "boudary shift anomaly" was related to the unexpeced offset measured connecting both ADC inputs to the same pin, I guessed that using built in system offset calibration could be a possible turnaround.

    Here are the results of the tests I did yesterday on this issue: I modified the adc init software in this way:

    - reset device

    - write to ACR to disable input buffer and clear the range bit

    - clear ODAC

    - run self gain calibration

    - write to MUX to connect both pos and neg adc inputs to the same pin (I chose the half-way voltage point)

    - run system offset calibration

    - wait 600ms

    - write to ACR to set the proper range=1 setting

    - do a dummy adc read to purge buffer

    Following this procedure the "boundary shift anomaly" seems to be completely disappeared.

    This maybe would be helpful for other users.

    In any case I would be happy to have an explanation of what is happening, this would make me to feel more confortable on my device!

    My feeling is that in the real world there is a sort of "common mode" voltage shift that is present on both adc inputs with respect maybe to the reference source. I designed the ground planes as much carefully as possible (see picture). It was not possible to completely avoid ground path asymmetries, but the biggest path difference affects the sensor input ground while the ground paths for both the Vref voltage generator and the "half-way" voltage point are very short so I cannot explain how the offset shift is the same if I measure it connecting both adc inputs to the sensor input and also connecting them to the "half-way" voltage point (PCB layout sketch attached).

    So, analyzing the PCB I would maybe justify an offset change when connecting both adc inputs to the sensor inputbut not the same when connecting them both to  the "half-way" voltage point.

    Is there any other reasonable explanation in your experience?

  • I need to correct the software management of the ADS1243 the right sequence is:

    - reset device

    - clear PGA

    - write to ACR to disable input buffer and clear the range bit

    - clear ODAC

    - run self gain calibration

    - write PGA

    - run self offset calibration

    - write ODAC if required

    - write to ACR to set the proper range=1 setting

    - write to MUX to connect both pos and neg adc inputs to the same pin (I chose the half-way voltage point)

    - run DSYNC

    - wait 300ms to ensure a new conversion is done

    - run system offset calibration

    - wait 600ms

    - do a dummy adc read to purge buffer

    - write to MUX to connect pos and neg adc inputs to sensor and half-way voltage point

    - run DSYNC

    - wait 300ms to ensure a new conversion is done


    If I do run the system offset calibration without having previously run a self offset calibration the anomalous offset shift happens again, why?

    I also have an additional question: in my design I was thinking to detect the -DRDY falling edge by software (reading the ACR register). Unfortunately the width of the logic level high pulse is too short (about 30 usec) and having a slow SPI bus I am not able to ensure the falling edge is detected.

    In order to minimize the errors related to the changes in mux settings is it correct to issue a DSYNC command just before the mux is changed and then wait for the conversion time before reading ACR and the adc uot register?

     

  • One last-minute additional information.... enabling the input buffer heavily reduced the residual offset and even the noise performances seem to be improved.

     

  • fbj,

    You have asked a lot of questions, and I think that maybe you're beginning to see some of the interactions that take place at the 24-bit level.  For example, if the reference is noisy, it will affect your performance.  If your ground is poor it will affect your performance.  If digital signals cross with analog signals it will affect your performance.  These are usually the most critical areas, but there are others. 

    Another example is input impedance.  If you use gain (and even if you don't it is just more obvious with gain), you will drop the input impedance which will create a voltage drop across the input resistor.  To reduce that problem a buffer was added to the input stage to increase the input impedance.  You saw the positive results of that in your testing.  The drawback is that the buffer reduces the overall range of measurement.  Some customers add there own external buffer to increase the range, or they make sure that if they use the ADS1243 buffer they maintain the input within the specified range.

    You provided a layout, and I'm assuming that your board is two layer.  I'm not able to tell if you are crossing any analog and digital signal lines, but as I mentioned earlier that can be a big problem.  Another thing, you really don't have a ground plane.  You have some polygon fill areas connected by traces.  This might be ok for 16-bit performance, but to maximize performance at the 24-bit level, there should be a solid ground plane.  Obviously, to do that you would have to increase your board layer count.

    So, there are trade offs.  Maybe the best trade off for this situation is to use the internal buffer and make sure that the sensor output stays within the range of the buffer.  It appears that the lower impedance creates an offset with current going through the mux.  The current path will shift as you pass through the boundary and that is why you see big shifts as you pass from one side of the voltage at AIN- to the other at AIN+.

    Best regards,

    Bob B