DAC8775: DAC8775 Initialization without internal buck-boost converter

Howdy Wahib,

If I understand correctly, you are trying to locate an init sequence for setting Channel A to 1mA, is this correct? If so, I've created a pseudo-register sequence that may be helpful.

*Please verify a Hardware Reset Before writing to Registers*
*This does not include setup of internal DCDC*
SPIWrite(0x01, 0x0001);//Software Reset
SPIWrite(0x02, 0x0012);//Enable Reference, Power-off Condition, change to High-Z for VOUT and IOUT
SPIWrite(0x03, 0x0020);//Select DAC Channel A
SPIWrite(0x04, 0x000F);// set for 4 to 20mA range
SPIWrite(0x04, 0x100F);//Enable output
SPIWrite(0x05, 0x8000);//Write DAC Data Register value to mid-scale

Best Regards,
Matt

This is the initialization code, but still doesn't work!

void DAC8775_init()
{
// Initialize SPI
SPI_A0_init();

// Initialize ALARM pin as input with interrupt
P6REN |= DAC8775_ALARM_PIN; // Enable internal resistor
P6OUT |= DAC8775_ALARM_PIN; // Set resistor as pull-up
P6DIR &= DAC8775_ALARM_PIN; // Set pin as input

P6OUT &= ~(DAC8775_CLR_PIN + DAC8775_LDAC_PIN + DAC8775_RST_PIN); // Initialize as LOW
P6OUT |= DAC8775_CS_PIN; // Initialize as HIGH
P6DIR |= DAC8775_RST_PIN + DAC8775_CS_PIN + DAC8775_CLR_PIN + DAC8775_LDAC_PIN; // Set as output pins

// Set RST as HIGH
P6OUT |= DAC8775_RST_PIN;

DAC8775_writeToRegister(DAC8775_RST, 0x0001); // Software Reset
DAC8775_writeToRegister(DAC8775_RST_CONFIG, 0x0012);// Enable Reference, Power-off Condition, change to High-Z for VOUT and IOUT
DAC8775_writeToRegister(DAC8775_SELECT_DAC, 0x0020);// Select DAC Channel A
DAC8775_writeToRegister(DAC8775_CONFIG_DAC, 0x000F);// Set for 4 to 20mA range
DAC8775_writeToRegister(DAC8775_CONFIG_DAC, 0x100F);// Enable output
DAC8775_writeToRegister(DAC8775_DAC_DATA, 0x8000); // Write DAC Data Register value to mid-scale
}

void DAC8775_writeToRegister(uint8_t registerAddress, uint16_t value)
{
DAC8775_select();

SPI_A0_sendByte(registerAddress);
SPI_A0_sendByte((value & 0xFF00) >> 8);
SPI_A0_sendByte(value & 0x00FF);

DAC8775_deselect();
}

Hi Wahib,

It may be better for our debugging efforts to receive an oscilloscope capture of one of the transactions above. This will allow us to verify if it meets the timing specifications shown in our datasheet. Additionally, a schematic of the solution will also help to see if the part is setup and configured properly.

Best Regards,
Matt

Hi,

This is the schematic:

Hi Wahib,

There are several potential issues with the schematic you've supplied. I've provided an overview of my feedback below:

• For channels that are not in use, you must ensure that their respective PVDD and PVSS pins are connected to AVDD and GND respectively.
• DVDD pin should have some form of bypass capacitance, we typically list 0.1uF
• Add 0.1uF bypass capacitance near REFOUT/REFIN pins
• Do you know the state of RESET, LDAC, and CLR at startup?
• After setting the DAC Register, have you asserted /LDAC?

Please also provide a complete SPI transaction with the following signals:

• SDI, SCLK, SYNC, LDAC

Best Regards,

Matt

Howdy Wahib,

I'm glad that you were able to determine a solution. Please be aware that an LDAC before or after /SYNC is asserted high are both valid conditions, but you may need to refer to the datasheet for timing requirements -- this is shown in page 13 of the datasheet. Additionally, you can permanently tie LDAC to GND if you wish to immediately update the output after SPI transactions.

Best Regards,
Matt