DAC3164: IO Test Clarification

Hello Dan,

Any update on this?

Thanks,

Royce

Hi Royce,

In the thread that you pointed to, there is a power point included that helps to describe how the input pattern file should be formatted to address both channels.

4540.DAC3174 Pattern Test Feature.pptx

If you read the notes in the last slide, it mentions that the first column (of the input data pattern file) will map to channel A, and the second column will map to channel B.

Additionally, whether you are operating in SDR or DDR, based on the data clock, should not impact the operation of the pattern test since the DAC is a single sample bus device that uses de-interleaving to break out channel A/B from the input data pattern. The pattern test does require that sample0 of the input pattern be aligned with the rising edge of SYNC, but does not required the data clock. From the data sheet schematic shown below, you can see that the pattern test occurrs before the de-interleaving.

Regards,

Dan

Hi Dan,

Based on what you are saying, the pattern should be applied as shown below for Dual Channel DDR mode (setup/hold times are not accurately depicted). Can you please confirm?

You said:

The pattern test does require that sample0 of the input pattern be aligned with the rising edge of SYNC, but does not required the data clock.

Can you elaborate on what you mean by "does not require the data clock"? It looks like the test pattern circuitry runs in the data clock domain and therefore would require the data clock to be running.

Thanks,

Royce

Hi Royce,

Sorry for the confusion. I was attempting to quote the DAC3154 datasheet, and meant to say that the Sync needed to be aligned to sample 0, but the data clock does not.

Also, could you share with me where you got the Data Clock, SYNC and Data diagram? I think this would be helpful if it were in the data sheet.

Regards,

Dan

Hi Dan,

I created the timing diagram using a free tool called WaveDrom, with the JSON below. Does the diagram correctly depict how the test pattern should be applied?

{
  head: {text: "DAC3164 IO Test Pattern Timing - Dual Channel DDR Mode"},
  signal: [
    {name: 'DATACLKP/N' , wave: 'n....', period: 2 },
    {name: 'SYNC', wave: '01xxxxxx01x', period: 1, phase: 1},
    {name: 'DATA[11:0]', wave: '==========', phase: 1,data: ['PATT_7', 'PATT_0', 'PATT_1', 'PATT_2', 'PATT_3', 'PATT_4', 'PATT_5', 'PATT_6', 'PATT_7', 'PATT_0'],},
],
  config: { hscale: 2 }
}

Thanks,

Royce