HI Team,
We’re feeding in 160MHz and bypassing the DAC PLL.
The SerDes rate is set to half-rate and MPY is set to 10 – thus we’re expecting to run at 20 x 160MHz = 3200MHz
I’m assuming this means that the SerDes VCO is running at 1.6GHz which is just OK; I would appreciate a block diagram of the SerDes PLL if you have one.
I have attached a spreadsheet showing the register values we’re loading – column E is the pertinent one in each case.
Thanks for your support and I look forward to hearing from you.
