ADS54J60EVM: ADS54J60 initialization

Hi Andrei

Our team is looking into your questions.

Someone will respond soon.

Best regards,

Jim B

Andrei,

Do you press the board reset after the LMK is configured but before loading the ADC?

What reference clock frequency does the ZCU102 require? You may need to change one of the clock output dividers from

"LMK_Config_Onboard_819p2_MSPS.cfg" to accomplish this.

1.  I don't see CGS sequence on the waveforms (i.e. bcbcbc) and SYNC~ never gets high. However if I select Link Layer Testmode "Constant K28.5" manually in the GUI the sequence passes succesfully. Moreover, If I select "Repeating ILA" after ADC configuration, there are several beats of bcbcbc -> SYNC~ goes high ->  ILA passes ok.

Not sure why this is. Are you seeing valid ILA parameters?

The question is why the ADC doesn't go through its initialization sequence in a normal mode? Why everything (at least initialization) seems ok only in a testmode?  I guess this is similar to this message

http://e2e-uat.ti.com/support/data_converters/high_speed_data_converters/f/68/p/585786/2152928#2152928

 This is not an issue with our Altera based capture card. What is the status of the LED's on the ADC EVM?  

2. What is the purpose of CLK_LAO_0P/M clock?  ZCU102 derives all the necessary internal clocks from FPGA_JESD_SYSREFP/M, particularly for SERDES operation and user logic clocking (rxclkout). So do I need to use CLK_LAO_0P/M?

Xilinx generated some early firmware that required a core and reference clock when using the VC707 and KC705. That is what this was used for. The Ultra-scale platforms do not require this.

3. Why N-parameter in the ILA sequence is 13 (i.e. resolution = 14 bits)?  It should be 15 for ADS54J60.  Can you send a screen shot of the label marked on the ADC package? Can you also send a screen shot of the ILA data from Chipscope?

Regards,

Jim

Hello Jim

Jim Seton said:

Do you press the board reset after the LMK is configured but before loading the ADC?

Yes.

1. Load LMK_Config_Onboard_819p2_MSPS.cfg

2. Check the PLL2 led

3. Press SW1

4. Load ADS54J60_LMF_8224.cfg

The reference clock (i.e.FPGA_JESD_SYSREF) is 204.8 MHz and this clock is required by ZCU102 for its PHYs. The line rate is 4.096 Gb/s

The following are the screenshots from analyzer.

1. LMK has been loaded with LMK_Config_Onboard_819p2_MSPS.cfg. ADC reset pressed. ADC has not been configured:

2. The moment when the ADC configuration file has been loaded. Note, that there are no CGS symbols.  SYNC is always low

3. The moment when I manually select "Repeating ILA" in the GUI. Note, there are "bcbcbcbc" beats, SYNC goes high and ILA starts.

Here are parameters I got from the ILA gt0_rxdata:

Jim Seton said:

Can you send a screen shot of the label marked on the ADC package?

I don't have it right now but I wrote down the PN of the chip : AZ54J60, TI 594, ZRFK, G4.

I guess, "N" value from ILA should be F, not D, am I right?

Andrei,

There was a register setting missing in the LMK config file you are using that is not turning on SYSREF to the ADC. Please try your tests with this new file attached.

Regards,

Jim

4405.LMK_Config_Onboard_819p2_MSPS.cfg 

Thank you, Jim

I'll try as soon as I get the hardware

Could you please confirm that no changes are needed in ADS54J60_LMF_8224.cfg which is supplied with GUI 1.4 ?

Any thoughts about N-value in the ILA sequence? Why is it xD?

Hello.

I've just tried the config you provided with the GUI 1.8, the waveforms haven't changed, There is still no CGS rigth after configuring the ADC while SYNC is low. I see CGS and ILA only after selecting "repeating ILA" in the GUI. The most confusing thing is that the ADC sends K28.5 only if testmode is selected.  It has no reaction on SYNC pulled low. 

What could be the reason that the ADC doesn't send K28.5 when SYNC is low?

Jim Seton said:

There was a register setting missing in the LMK config file you are using that is not turning on SYSREF to the ADC.

SYSREF is enabled now in 4405.LMK_Config_Onboard_819p2_MSPS.cfg, BUT,  it is still disabled in ADS54J60_LMF_8224.cfg.

That's why I'm asking you about the validity of the ADC config file.

Here is the config : 0272.ADS54J60_LMF_8224.cfg