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ADC12DJ3200: Need information about the speed

Amin Amiri
Prodigy 40 points
Part Number: ADC12DJ3200
Other Parts Discussed in Thread: , LMK04828

Hi all, 

I'm interested in the ADC12DJ3200 but need to know if used as one channel at 6.4 GSPS, will this speed be real-time or interpolated? I need to sample a L-band signal 950 - 1950 MHz at high speed and wondering if this card can do it. 

Many Thanks,

Amin

  • 0
    TI__Mastermind 44680 points

    Hi Amin

    The output data stream is not decimated or sub-sampled in any way.

    The Nyquist bandwidth is 3.2 GHz in that 6.4 GSPS condition.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 40 points

    Hi Jim,

    I see. I'm just concerned that there shouldn't be any phase delays introduced. I'm interested in looking at phase differences of multiple channel signals coming in. Also if I use one channel of the ADC card, can multiple ADCs card be synced? 

    Regards,

    Amin

  • 0 in reply to Amin Amiri
    TI__Mastermind 44680 points

    Hi Amin

    It is possible to synchronize multiple ADC12DJ3200EVM boards with low skew but doing so requires supplying phase aligned reference clocks to both boards and additional triggering modes of capturing data. The best way to do this is to design a new board with a common clock system driving multiple ADC devices which are connected to a single FPGA data receiver.

    The TI Design available at the link below shows one example of clocking 2 of the ADC EVMs in a synchronized way:

    http://www.ti.com/tool/TIDA-01021

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 40 points

    Hi Jim, 

    As I understand, the clocking ref evaluation board is not for sale, is there any other evaluation board readily available that can do the job? So say for a 4 channel solution, I will need x2  ADC12DJ3200EVM, x2 TSW14J56EVM and x1 clocking ref board. Will this setup need anything else to simultaneously and synchronously sample and capture the data from all 4 channels?

    Thanks,

    Amin

  • 0 in reply to Amin Amiri
    TI__Mastermind 44680 points

    Hi Amin
    That should be all you need for hardware.
    You will need to modify the EVM clocking configuration with some component rework and register setting changes to get phase matching between the ADCs. Using the standard EVM will result in an upper limit on the ADC clock rate that is somewhat below 3.2 GHz. You will need to use the LMK04828 as the ADC clock source, and it has an upper PLL VCO limit of 3080 MHz.

    The ADC12DJ3200EVM+TSW14J56EVM combination has limitations on maximum JESD204B data rate of around 10.8 Gbit/sec. This will limit the maximum ADC clock rate in the 12 bit modes of operation (JMODE0, JMODE2) to 2.7 GHz clock rate. This combined with the limitations of the LMK04828 VCOs will set the maximum practical clock rate for this synchronized configuration to around 2.5 or 2.6 GHz.

    Regards,
    Jim B