Hi,
I have received a question about clock jitter of ADS 1672 from my customer.
Q1.When using oversampling,is it necessary to pay attention to CLK jitter?
Q2.If not so,what is the maximum acceptable jitter value of the external clock input(CLK) to the ADS1672?
Best regards,
Seishin
Hello Seishin,
Thanks for your interest in our ADS1672!
The answer really depends on your application noise requirement. As with all noise sources, the noise from clock jitter only matters once it begins exceeding or dominating the inherent quantization and thermal noise in the ADC itself.
For oversampling converters, the impact of CLK jitter is reduced compared to non-oversampling or Nyquist converters. Below is an equation to help you estimate the ideal (or best-case) noise performance of an ADC based solely on the clock jitter spec and the input signal frequency. Notice that for oversampling converters, the theoretical best SNR performance is improved by a factor of 10*log(OSR).
Best Regards,
