Hi,
I am using DAC904E to generate signal for active noise cancellation. A Xillinx Spartan 6 FPGA is interfaced to DAC904E. The DAC904E is configured the same as the "TYPICAL CONNECTION CIRCUIT" on page 4 of the datasheet. A low pass filter with cut-off frequency 2 MHz is placed at the DAC output. The clock is generated from FPGA to DAC at 100 MHz. The output signal is single frequency at 100 kHz or 1 MHz.
My issues are
1). The noise of the DAC output signal (at 100 kHz) increases significantly, when the output signal amplitude increases. Could you please tell me which parameters of a DAC lead to this issue, e.g. INL, DNL, glich, jitter, etc?
2). The noise of the DAC output signal also increase when the signal frequency increases from 100 kHz to 1 MHz. Could you please tell me which parameters of a DAC lead to this issue as well?
3). Could you pliz recommend solutions, e.g. a better DAC, filtering, pll etc on these issues?
Thank you very much.
Yifei