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DAC904: E

Part Number: DAC904

Hi,

I am using DAC904E to generate signal for active noise cancellation. A Xillinx Spartan 6 FPGA is interfaced to DAC904E. The DAC904E is configured the same as the "TYPICAL CONNECTION CIRCUIT" on page 4 of the datasheet. A low pass filter with cut-off frequency 2 MHz is placed at the DAC output. The clock is generated from FPGA to DAC at 100 MHz. The output signal is single frequency at 100 kHz or 1 MHz.

My issues are

1). The noise of the DAC output signal (at 100 kHz) increases significantly, when the output signal amplitude increases. Could you please tell me which parameters of a DAC lead to this issue, e.g. INL, DNL, glich, jitter, etc?

2). The noise of the DAC output signal also increase when the signal frequency increases from 100 kHz to 1 MHz. Could you please tell me which parameters of a DAC lead to this issue as well?

3). Could you pliz recommend solutions, e.g. a better DAC, filtering, pll etc on these issues?

Thank you very much.

Yifei

  • Yifei,

    It is a bad idea to use the FPGA as a clock source as the phase noise on this signal is usually bad. Can you try using an external filtered clock source to get a base line for the board?

    Regards,

    Jim

  • Hi Jim,

    Thanks for the reply. Yes, I know a external clock distributer reduces the clock phase noise a lot. I had tested the FPGA SP6 and DAC 904E with a external clock distributer. I also put a external voltage reference to DAC 904E. But the issues above remains.

    I am not sure whether a higher resolution or speed DAC is needed, or some other key features of a DAC were missed. Thank you.

    With best regard

    Yifei
  • Yifei,

    I would suggest you trying running your setup to match a data sheet test plot to see how close you come. If you are way off, then you definitely probably have issues with either clock jitter, power, or filtering. If you are within a couple of db's, then that is probably as good is it is going to get with your setup.

    Regards,

    Jim