ADS1174: Daisy-chaining: timing limitation and chronogram

Hello Matthieu,

Thanks for your post! Is this by chance related to Simon's post?

In the "Sample Aperture Matching" section, we are referring the modulator sampling frequency at the input of the ADC. The modulator in each channel is running off of the same divided version of the master clock (the exact ratio depends on the MODE setting). The ADS1174 will have the same typical aperture delay as our 24-bit version, ADS1274, which is about 500ps (that datasheet was updated more recently). The channels within each ADS1174 device will be synchronized automatically to the same modulator clock cycle within that typical aperture delay.

However, the exact aperture delay seen by one ADS1174 device may be different than another ADS1174 in the same daisy-chain. As long as you have pulsed their respective /SYNC pins together, you can expect them to be synchronized within one master CLK cycle. This assumes that your layout does not introduce significant delays between the arrival of CLK to the ADS1174 on one board and the arrival of CLK to the ADS1174 on your other board.

The setup time is simply the time required for the next bit to be valid before the rising edge of SCLK latches the data. This delay will not affect your channel synchronization. The only concern is that, if your SCLK is not clean or has an excessive amount of skew, it may cause you to misread data from devices down the chain. Otherwise, you should not notice any break or delay between data of multiple devices as you read the data from DOUT1 of the master ADS1174.

I believe there might be a typo in the DOUT section that describes the MSB propagation to DOUT. If I recall correctly, it is actually the rising edge of FSYNC which shifts out the MSB (which matches the description in the ADS1274 datasheet). The falling edge of SCLK should be synchronized to the rising edge of FSYNC according to the timing diagram. The subsequent rising edge of SCLK will then latch in the MSB.

Best Regards,

Hello Ryan,

Thank you very much for your answer! I think my question and Simon's are just partially related. I think he's more looking to synchronize multiple ADS1174 with clocks signals generated by different GPS devices on different boards. My question is more about synchronizing multiple ADCs with the same CLK signal but with significant delays between them.

Your post helped understand many things but I still have questions.

Ryan Andrews said:

This assumes that your layout does not introduce significant delays between the arrival of CLK to the ADS1174 on one board and the arrival of CLK to the ADS1174 on your other board.

Actually, I am trying to define the maximum length of cable I can use between the two boards i.e., the maximum delays that can occur between the signals on the two (or more) ADS1174 (DIN/DOUT, CLK, SYNC). I am assuming this delay should be a fraction a the clock's period?

Regarding the last paragraph of your answer, the timing characteristics on page 8 of the ADS1174 datasheet shows t_MSBPD as "FSYNC rising edge to DOUT MSB valid (propagation delay)". So I think you are right, there is maybe a typo in the DOUT section.

Sincerely,

Matthieu

Hi Matthieu,

Thanks for clarifying. I still have some doubts about the setup you're aiming to achieve.

Are you daisy-chaining two or more devices with significant distance between them? Or are you daisy-chaining local groups of devices that are close together, but the groups of devices may be far apart and you want them all to be synchronous? Are all devices using the same SPI bus? If you could, please share a block diagram of how you plan to arrange the ADS1174 devices in your system relative to each other and to the host MCU.

The aperture delay between channels of different devices will be dependent on the delay between the arrival of their respective CLK signals. FSYNC, CLK, and SCLK should be coming from the same source and remain synchronized (CLK and SCLK falling edge aligned to FSYNC rising edge), so that shouldn't be an issue as long as their respective trace lengths are well matched.

The key delays to pay attention to with daisy-chained devices are the setup and hold times for DIN (tDIST and tDIHD). As long as the traces between DIN and DOUT of neighboring devices is kept short, you shouldn't have to worry about corrupting the data from downstream devices.

Best Regards,

Hi Ryan,

Thank you for your answer.

Ryan Andrews said:

Are you daisy-chaining two or more devices with significant distance between them? 

Yes, exactly. I am trying to evaluate what is the maximum distance I can have between two or more ADS1174. Below is a block diagram of the setup I am talking about. All devices are connected together with a cable of length d (greater than 1,5 meters), so one cable between devices C and B and one cable between devices B and A. The clocks are generated in the device A and sent to the other device through the cables. The cables introduce a significant delay in the signals transmission, but if this delay is kept short enough compared to the clock period, it will have no impact on the operation of the system? You said in your previous post that the critical timings with daisy-chained devices are the setup and hold times for DIN (tDIST and tDIHD), so as long as those timings are respected, the system below should work, right? Additionally, does it mean that lowering the clocks frequency should allow to increase the cable length even more?

The configuration is: Frame-Sync, TDM, Fixed Data position. 

I sincerely thank you for your help.

Best regards,

Matthieu