This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12D1600RF: ADC12D1600RF Measured ENOB

Part Number: ADC12D1600RF

I have an ADC12D1600RF that I'm clocking at 1.28 GHz in DES mode (sample rate = 2.56 Gsps real).  I'm generating the clock signal with an Agilent signal generator with a high stability time base.  I'm generating a 1 GHz tone to be sampled with another Agilent signal generator with a high stability time base.  The two signal generators are phase locked.  I measure an effective number of bits (ENOB) of 5.5 for the 1 GHz tone.  I was careful to calibrate the ADC prior to collecting data.  I see all of the spurs identified in SLAA617 in the power spectrum of the collected data.  The largest are the harmonic spurs.

I'm wondering why the ENOB I'm measuring is much less than the ENOB published in the ADC12D1600RF data sheet.

SLAA617 lists several on-chip tools for reducing spurs related to interleaving.  SLAA617 suggests external dithering to minimize the harmonic spurs.

Can Texas Instruments provide more information about how they calculated ENOB in the ADC12D1600RF data sheet?  Specifically, was dithering used when measuring ENOB?

I attached a Word document containing a plot of the power spectrum and identifying each of the spurs and their source.  Does anyone have helpful suggestions how I can achieve an ENOB closer to what is published in the ADC12D1600RF data sheet?

Regards,

Scott

ADC12D1600RF Spurs.docx

  • Hi Scott

    Do you have a band-pass (or low-pass) filter on either the ADC input signal or clock?

    Many high quality low jitter signal generators will have significant power at harmonics of the fundamental frequency. For that reason it is important to eliminate those harmonics before presenting them to the ADC input (very important). The harmonics generally cause less problems on the clock input, but some benefits are generally seen by adding a filter to that path as well.

    Try putting a filter on the ADC input signal and see if the harmonic spurs clean up. I think this should get the SINAD and ENOB performance back into the expected range.

    A band-pass filter at the signal frequency is the best approach, but a low-pass filter with cutoff between the fundamental and 2nd harmonic can also provide significant benefit.

    Your analysis of the SI and INT tones is correct.

    The SI fixed frequency interleaving tones caused by offset mismatch between interleaved sub-ADCs can be minimized by proper calibration of the ADC.

    The INT-2 tone is caused by residual timing and/or gain mismatch between the 2 interleaved ADCs (I and Q). This one can usually be reduced by re-calibrating the ADC to optimize gain matching, and adjusting the DES Timing Adjust register setting of the ADC to optimize interleave-by-2 sample timing.

    The INT-1 and INT-3 tones are caused by residual timing and/or gain mismatch between the 4 interleaved sub-ADCs (I1, I2, Q1, Q2). To minimize the energy of these tones ensure the ADC is calibrated at the stable operating condition (clock rate, junction temperature).

    Best regards,

    Jim B

  • Hi Scott
    Let me know if things are resolved or not.
    One other reason that harmonic performance would be degraded is if the ADC is not properly calibrated at a stable operating point.
    Once the ADC is powered up, configured and the input clock is stable, wait for the ADC temperature to be near the final temperature (within 15-20 degrees C) and then recalibrate the ADC. Then check the performance.
    Best regards,
    Jim B
  • Hi Jim,

    Thank you for the helpful advice. I'm waiting for the band-pass filters to be delivered. I verified on the spectrum analyzer that the signal generator is indeed producing harmonics.

    Regards,
    Scott
  • The addition of analog filters to the clock and to the tone being digitized significantly reduced the harmonics created by the signal generators. The ENOB I measure at 1000 MHz increased from 5.5 to 8.1 after this change. The harmonics are no longer the largest spurs in the spectrum. The spurs at (fs/2 - fin) and (fs/2) are now the largest spurs. I always use calibration, and I re-calibrate frequently just to play it safe. My next step is to use the non-calibration techniques available inside the ADC to reduce the (fs/2 - fin) and (fs/2) spurs.

    Regards,
    Scott