Dear sir,
We are using DAC38J82 at DACCLK - 2.4GHz bypassing the DAC PLL. Rate - Half rate , Interpolation - x2. Line rate - 6Gbps
My serdes reference clk divider is 4. so, Serdes reference frequency is 600MHz. and mutliplier factor is 5. So, Serdes PLL output frequency is 3Gbps which is half of Line rate.
Now , I changed DACCLK to 840MHz, Line rate = 4.2Gbps. changed the serdes reference clock divider to 2, - Reference clock is 420MHz., MPY -5 To meet the requirements of half rate.
In this case, SYNC is not asserting (i.e, high). It is continously toggling. whereas in 2.4GHz SYNC is continuous high.
Apart from changing the serdes reference divider value any other configuration to be changed.
My doubt,
1. How to calcuate the jesdclk-div value ?
2. What is buswidth?
Regards,
Jaya Bharath
