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ADS1271: SYNC pin used in Frame-Sync mode

user3907675
Prodigy 10 points
Part Number: ADS1271

Hi，

Recently, I work on a project, which need a lot of ADS1271 chip work together. All of the ADS1271 operates in frame-sync ,low-power mode. I use the same SYNC pin to synchronized the ADS1271,so that synchronous sampling, the SYNC pin of all ADS1271 controlled by MCU GPIO. In the datasheet , when the SYNC line is sampled low, the ADS1271 halts the conversation process and resets the digital filter. 

I have some question. When I set the SYNC pin low to synchronized  the ADS1271, all of the ADS1271 need to reset，I don't hope such operates. I hope to achieve the function that: the SYNC low pluse generates in periods, and the periods meets the max counter of the digital filter.So that  if one of the ADA1271 is the not synchronized with others, I only need to reset this ADS1271 through set the SYNC pin low,and others ADS1271 do not need to reset.Thus all of the ADS1271 still synchronized. I think if the period of the digital filter or the max counter of the digital filter  is know,  the function could achieve,but I am not sure and the datasheet do not say that. I hope to get your help,thank you very much.

  • 0
    TI__Guru 66166 points

    Hello,

    Thanks for your interest in our ADS1271!

    Are you trying to control each /SYNC pin with a separate GPIO on your MCU? The easiest way to synchronize all devices is to tie all /SYNC pins together and control them with one common signal from the MCU. If you synchronize all ADS1271 devices after the system starts up, you should expect that they will remain synchronized after the /SYNC pulse is issued.

    If you needed to issue another /SYNC pulse to only one device, you would have to determine exactly which master clock falling edge corresponds to the beginning of the next data rate period (i.e. the next frame). In other words, you would need to take /SYNC high at least tSCSU seconds before the master clock falling edge which aligns with FSYNC rising edge (see page 7 for CLK falling edge to FSYNC rising edge requirement, tCF). I see this as being very difficult and perhaps impractical to implement, but it should be possible.

    Best Regards,