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ADS4146: dac3151,ads4146 connection

dor ben david
Prodigy 40 points
Part Number: ADS4146
Other Parts Discussed in Thread: DAC3171

Hello all ,

I want to connect an 14 bit adc (stated in the headline)with parallel lvds output to a 14 bit dac (stated in the headline) that works with serial input . 

is it possible ? if not what other option do i have with ti products with the same sample rate and that supports lvds ?

Thanks for the help .

  • 0
    TI__Mastermind 43910 points
    Hi
    It is not possible to directly connect a parallel output ADC to a serial input DAC.
    Even connecting devices with similar interfaces could be fairly challenging. Normally the ADC and/or DAC devices will be connected to an FPGA or ASIC which performs some processing on the captured ADC data or output DAC data.
    What sample rate are you trying to achieve?
    What is the maximum frequency of the signal you are trying to capture/regenerate?
    Regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    Prodigy 40 points


    Hey Jim ,

    so what other ADC do TI have with the same bit number and sample rate that supports serial ands lvds output ?

    We are basicly looking for some adc that will match the dac3171 .

    We are planning on eventually using an fpga but how can we test that before all the fuss ?

    thanks .

  • 0 in reply to dor ben david
    TI__Mastermind 43910 points

    Hi

    For full resolution that DAC requires an SDR (Single Data Rate) input clocking scheme, with one rising edge of DATACLK for every data word read in. All ADCs I have located that sample at 14 bits and 500MSPS use DDC output data clocking. Data is captured into the FPGA or ASIC on both rising and falling edges of DCLK. For that reason it isn't possible to connect this parallel DAC directly to a parallel output ADC.

    The DAC3171 has a 7 bit mode that supports DDR data clocking (See Figure 3.), so that might work but would be reduced resolution. It can still be tricky to get the data to data clock timing optimized for data capture at 500 MHz data rates. That's why it would be best to put an FPGA in between the ADC and DAC to help manage data and data clock timing.

    You can test the performance of the DAC and ADC individually by using the TI evaluation tools.

    But it sounds like want to stream data continuously from the ADC to the DAC to prove your system concept. Unfortunately that is something that can't be done with the EVMs.

    Best regards,

    Jim B