• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 3 answers
  • Subscribers 47 subscribers
  • Views 903 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC3151: DACCLK

David Zhao
Intellectual 1820 points
Part Number: DAC3151
Other Parts Discussed in Thread: CDCE62005

Hi

For DAC3151, please help with below questions. Thanks!

1.What is the relationship of DATA CLK and DAC CLK? If data rate is 400MHz, then DATA CLK and DAC CLK are both 400MHz?

2.Is DATA CLK and DAC CLK must from same clk source?

3.Customer tend to provide DAC CLK from FPGA. Is it ok?

4.FPGA CLK output is LVDS, but DAC CLK needs LVPECL. Is it ok?

Regards

David

  • 0
    TI__Mastermind 44300 points
    Hi David
    DATACLK should be an LVDS clock provided by the FPGA to enable latching of of data into the DAC.
    DACCLK must be a low jitter high slew rate clock. It is used to create the DAC output signal, so jitter is important if a good quality DAC output signal is desired. This requirement means that the FPGA should not be used to create this clock.
    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    TI__Intellectual 1820 points

    Hi Jim

    Thanks for response for question 3 and question 4. How about below questions? Thanks a lot!

    1.What is the relationship of DATA CLK and DAC CLK? If data rate is 400MHz, then DATA CLK and DAC CLK are both 400MHz?

    2.Is DATA CLK and DAC CLK must from same clk source?

    Regards

    David

  • 0 in reply to David Zhao
    TI__Mastermind 44300 points

    Hi David

    The DACCLK is at the output sample rate of the DAC. As shown in the datasheet this clock should be created by a low jitter source like the CDCE62005 or LMK048xx. This same clocking device will send a clock to the FPGA for use creating the DATA and DATACLK timing.

    The DATACLK is a SDR (single data rate) synchronous to the DAC DATA being sent by the FPGA. See Figure 1 of the DAC3151 datasheet. Since the clocking mode is SDR, the DATACLK and DACCLK frequencies will be the same. The timing of this clock with respect to the data is critical, so both should be generated by the FPGA.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    TI__Intellectual 1820 points
    Hi Jim

    DAC3151 user guide shows DAC3151 pairs with TSW1400 to test. i dont have TSW1400 in hand now. Could I use TSW14J56 or TSW1266 or any other to replace? Thanks a lot!

    Regards
    David
  • 0 in reply to David Zhao
    TI__Guru* 91947 points

    David,

    Those other two boards you mentioned will not work. Your only other option is the low cost TSW1406EVM.

    Regards,

    Jim