ADS5463EVM: input clock

Hi Amir

1) SE clock input is readily usable with high quality signal generators. These configuration allows a high quality clock signal from the generator to be connected to the differential CLK+/- inputs of the ADC, which will give the best possible jitter performance, resulting in the best possible SNR.

2) The differential inputs are not intended to be accessible on the EVM.

3) FPGA generated clock signals will generally have higher jitter (from signal and power noise coupling, etc.) than can be used to achieve rated performance with the ADC. Please refer to the Clock Inputs section of the ADS5463 datasheet and Table 2, which lists the recommended RMS clock jitter for particular input signal frequency applications.

4) If you connect the single ended clock as shown in the ADS5463 datasheet then the device will function. The performance that is achieved will be a function of the CLK amplitude and jitter, and the input signal frequency.

5) The best way to drive the ADS5463EVM CLK input is using a good quality signal generator capable of 500 MHz and 1.5Vpp into 50 ohms. Another possibility is to use a clocking device EVM with similar capabilities. Something like the LMX2582EVM would be a good choice. The best way to drive the ADS5463 device inputs on a customer designed board is to use a clocking device with the required output frequency, drive level and jitter performance. A good place to start is the Clock Architect on-line tool available here:

http://www.ti.com/design-tools/signal-chain-design/clock-architect.html

Best regards,

Jim B