ADC12DJ3200EVM: External clocking at 4GHz and DC coupling

Apurva Gowda

Part Number: ADC12DJ3200EVM
Other Parts Discussed in Thread: ADC12DJ3200, , LMH5401, LMH3401

Hi,

I have a couple of questions about the ADC12DJ3200 and it's evaluation board capabilities.

The ADC12DJ3200 datasheet specifies a sampling rate of 6.4Gsps in single mode operation, however, the maximum clock frequency is specified as 3.2GHz. Is the 6.4GSps achieved through internal engineering? Does that mean a 4GHz clock cannot be used to achieve a sampling rate of 4Gsps?

2. We would like to DC couple our input signal to the ADC12DJ3200EVM. Are there any modifications that need to be done to the eval board? Also, do you have a recommended differential amplifier that has a flat gain over the entire 8GHz bandwidth?

Thanks,

Apurva S. Gowda

over 7 years ago

0 Jim Brinkhurst1 over 7 years ago

TI__Mastermind 44680 points

Hi Apurva

1. The 6.4 GSPS sample rate is achieved using JMODEs 0, 1, 4, 5 and 17. In these modes the single ADC input is sampled on both rising and falling edges of the input CLK.

2. The ADC can be driven with DC-coupled inputs by removing R1 and R4, and installing R180 and R179 (0 ohm resistors). Please refer to sheet 2 of the ADC12DJ3200EVM schematic: /cfs-file/__key/communityserver-discussions-components-files/73/6866.ADC12DJ3200_5F00_HSP001EVM_2D00_SCH_5F00_A.pdf The input signal applied to INA+ and INA- connectors should have a common mode voltage of 0V, and a differential voltage range of approximately +0.4V to -0.4V.

The highest bandwidth and performance fully differential amplifiers would be the LMH3401 (fixed gain) and LMH5401 (resistor set gain). These are not capable of covering the entire 8 GHz bandwidth, but are the best available from TI.

Best regards,

Jim B

0 Apurva Gowda over 7 years ago in reply to Jim Brinkhurst1

Prodigy 220 points

Thanks Jim. So if I clocked the ADC with a 2GHz sine wave in JMODE 0, it would sample at 4Gsps, is that correct?

0 Jim Brinkhurst1 over 7 years ago in reply to Apurva Gowda

TI__Mastermind 44680 points

That is correct. The clock amplitude must meet the requirements listed in the Operating Conditions table in the datasheet. The clock phase noise must be low (similar to the aperture jitter of the ADC) to ensure it does not compromise the sampling SNR of the converter.
Best regards,
Jim B

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ADC12DJ3200EVM: External clocking at 4GHz and DC coupling