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ADC12D1600RF: Algorithm to Calculate "I/Q Offset Adjust", "I/Q FSR Adjust", and "DES Timing Adjust" from Sampled Data

Scott Geaghan
Prodigy 70 points
Part Number: ADC12D1600RF

Does TI have an algorithm description or software for calculating the "I/Q Offset Adjust", "I/Q FSR Adjust", and "DES Timing Adjust" from sampled data?  If so, are they willing to share it with customers?

I'm recording a nearly full scale tone in DES mode.  The tone is phase locked to the sample clock generator.  Therefore, the frequency of the sampled data exactly matches the frequency programmed in the signal generator.  I choose a frequency that will produce an integer number of cycles in the recorded data.  I'm working on an algorithm that will automatically calculate the above mentioned register settings for optimal spur mitigation, but it would be nice if TI already has an algorithm they are willing to share.

Regards,

Scott

  • 0
    TI__Mastermind 44680 points

    Hi Scott

    Unfortunately I don't have a canned algorithm to share.

    I think your test signal is OK, and I would perform the optimizations in the following order:

    1. With ADC powered, configured and clocked, and at a stable operating temperature perform a calibration.
    2. Apply the test signal and fine-tune offset settings to match DC offsets. You could start with an estimated change based on typical offset stepsize and then do an incremental search to get the best final result.
    3. Fine-tune full scale range settings to optimize amplitude matching. A similar approach as used for offset should work here.
    4. Fine-tune DES timing adjust to minimize Fs/2-Fin timing spur. You need an initial adjustment step to determine which direction to go from midscale. Then a binary search of some type should work.
    5. Re-adjust full scale range settings to see if further reduction of Fs/2-Fin timing spur can be achieved.

    Best regards,

    Jim B