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ADS1262: ADS1262 Synchronization

Idan Ozana
Intellectual 480 points
Part Number: ADS1262
Other Parts Discussed in Thread: REF6050, ADS1274

Hi,

My name is Idan and I'm electronics engineer for the Israel Aerospace Industry (IAI).

 In my application I need to measure fully differential, 3V, analog inputs, at least 24 effective bits. Also, I need to sample three simultaneously ADC inputs and to since it with several similar cards (also 3 axis for etch card- 3 separated ADCs connected to the same FPGA on etch card- I have no problem to cope the SPI to three independent firmware). In order to do that, I thought to use the ADS1262 32-Bit, Precision, 38-kSPS (I'll us the ~10sps), Analog-to-Digital Converter (ADC) but in order to do that I need you to answer the following questions regard to the Synchronization between channels and between cards:

  1. How can I Synchronize the 3 independent ADC on the same card? Maybe using the same clock reference? (Thought the same FPGA…)
  2. How can I Synchronize between several independent cards?

Thanks,

Idan

  • 0
    TI__Mastermind 44680 points

    Hi Idan,

    Sure, I'd be glad to help answer those questions!
     

    First, synchronizing multiple ADCs requires that you use the synchronized clocks for all ADCs.
    Ideally, you'd want to have a single clock source routed to all ADCs (on the same card or on different cards). When using multiple clock sources, there is always the potential for clock jitter and drift to cause the clocks (and hence the ADCs) to get out of sync.Also, to avoid differences in clock phases between ADCs, you'll want to try to match the trace lengths of the clock signals from their source.

    Second, you'll need to issue a simultaneous START command to all ADCs to ensure that ADCs begin converting within the same clock period.
    This could be done either through hardware (using the START pin) or through software (sending the START1 SPI command). For the hardware START command, you'll want to try to match the START signal trace lengths. For the START1 SPI command, you'd need to have all FPGAs issue this command simultaneously, which may be difficult to do so I would likely recommend using the START hardware pin.

    For synchronizing ADCs across multiple cards, you might need to consider using a central clock source and GPIO control of the START pin (routed to each card from the main motherboard) to avoid possible differences in delays on each card.

    Additional notes:

    To measure up to and greater than 3V differential signals and achieve 24-bits effective resolution, you'll need to use a low-noise external reference source. I would consider the REF6050 (or any of the REF6x50 devices) or the the REF5050. Keep in mind that the ADC noise performance will degrade as you use higher data rates. Also, the reference noise will be a factor to consider for non-zero input signals, which is where the ADS1262 noise performance is specified (so that only the ADC's noise performance is specified). The RMS noise of your reference source will ADD to the ADC's RMS noise as:

    Total noise = sqrt( [ADC Noise RMS]^2 + ( [%FS] * [REF Noise RMS] )^2 )

    where [%FS] is a multiple that scales the reference noise based on how large the input sigal is compared to the ADC's FS range. At 100% FS, this multiple will be "1" to indicate that all of the reference noise will have an effect.

    To calculate REF Noise RMS, you'll need to know the approximate noise density of your reference source and the effective filter bandwidth of the ADS1262 at 10 SPS, for the particular SINCx filter you select. Refer to this Excel tool for assistance with determining these values: 

    Best regards,
    Chris

  • 0 in reply to Christopher Hall
    Intellectual 480 points

    Hi,

    First, thank you for your quick and detailed response!

    You say that in order to synchronize multiple ADCs I need to use the synchronized clocks for all ADCs- single master clock. I don’t understand exactly why… The sigma delta ADC need clock (fclk=7.3728 MHz for the ADS1262) to extract the modulation frequency for correct and accurate conversion (Fmod=Fclk/8= 921.6kHz). If the clock has let's say 100PPM drift- I don't think that that would affect my reading because the maximum deviation will be only one Fclk cycle (or max Fmod) until the next rising edge clock in which the modulator will sample the input data, Am I right? In other words, my claims is that if I'll drive two completely in Independent ADC's with  external sinus waveform, after even several days there will be no phase deviation between them, Am I right?

    If not…

    When focus on the one card only (three different ADS1262 ADC's routed to the same FPGA), can I use the ADS1262 devices in a single clock source configuration routed to all three ADCs? What is the max distance between the source and the ADC's? In the Layout Guidelines section is specifically recommended to place the crystal and load capacity directly on the ADC pins which cannot be done when working in a single clock configuration… What are the, most important parameters that I need to be aware when using single clock source to several ADC's? (max capacitance, length of the routed traces (will probably be different due to the physical distance between the ADCs, right?), the master clock driving capabilities and so on…  

    In addition, in the ADC1274 for example (my second ADC choice…) I can use the SYNC operation pin (active low) to sync between ADC's as it will reset the digital filter counters and data. Can I say that I can do the same with the ADS1262 RESET pin?  

    Thank's a lot,

    Idan       

  • 0 in reply to Idan Ozana
    TI__Mastermind 44680 points

    Hi Idan,

    If it is not a problem to let the ADC's get slightly out of synchronization, then you can certainly relax the clocking requirements. You can always bring the ADC's back into a fairly synchronized state by toggling the START pin to all of them at the same time. When restarting the conversions at the same time, all three ADCs will be synchronized to within 1 fclk period. From there, depending on how much clock drift exists between clock sources, you'd want to re-synchronize the ADCs every so often to bring them back to this fairly synchronized state. For low-frequency input signals, you probably wouldn't see much (if any) phase shift if your clock sources are stable...because the input signals are being over-sampled and averaged it would likely take a large number of fclks between ADCs to affect the result.

    Re-synchronizing the ADS1262 with its low-latency filter (1-4 conversion cycles settling delay) is probably not much of any issue in most applications. For the ADS1274 with a wide-bandwidth filter, its settling time is much longer (about 78 conversion cycles), which may be more problematic when wanting to maintain a continuous data "stream".

    If you do decide to route a single clock source to all three ADCs, you would want to try to:

    • still keep these traces as short as possible (to avoid transmission line effects)
    • avoid using vias (or keep vias to a minimum) when routing these traces
    • ensure these traces are routed above an (uninterrupted) ground plane layer
    • plan for transmission line impedance matching...I generally use back-matching (placing a ~50 Ohm series resistor near the sourcing pin) to absorb any signal reflections (assuming the trace is sized to have a 50 Ohm characteristic impedance).

    All of these guidelines will help to reduce parasitic inductance and improve the signal integrity of the clock signal.

    Did that answer your questions?

    Best regards,
    Chris

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