Hi,
We are using the ADC3443 to sample the output of an image sensor. The input will thus be DC-coupled, using fully-differential input buffers.
We would like to estimate the noise performance of the ADC under these conditions but the noise performance is always specified for high-frequency analog signals, while it is not exactly the case in our application. The signal is composed of successive voltage levels. Even if the transitions have a high-frequency content, we sample the signal when it is stable, i.e. at DC.
I thus have two questions :
- Is the S&H circuit in sample mode during the whole half-period of the sampling clock ?
- How can we calculate the noise performance (SNR, ...) of the ADC for a DC input signal?
Thank you for your help.
Best regards,
Lionel
