Hi,
I have a problem for proving mathematically the reality of obtaining better data acquisition performance when i inject clock to my data converter deferentially vs single-ended case. Can anyone introduce me a related technical document? As a second issue, i guess the clock distribution path of a data converter particularly the differential amplifier in the path have the major effect on the sampling performance merits like output rms jitter. I think that CMRR maybe a mathematically defined parameter related to my case but is this parameter measured value reported in any ADC or DAC datasheet? In fact i need to understand my application immunity range for applying differential or single-ended clock to data converters according to performance parameters like SNR or output rms jitter.
Best Regards
Moham
