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ADC12D1620QML-SP: Recommended Sample Clock

John Roy94
Prodigy 180 points

Part Number: ADC12D1620QML-SP
Other Parts Discussed in Thread: CDCM7005-SP

We are in the process of designing the sample clock circuit for the ADC12D1620QML device and would like to bread board a circuit. In our travels, we’ve been made aware (through app notes and lab testing) that the ADC can be sensitive to both jitter (aka phase noise) and harmonics relative to the sample clock input.

 

For the flight devices, is there a preferred way to provide the sample clock? We’re trading off using a PLL based solution vs. a jitter cleaner based solution. Is there a recommended part / topology?

  • 0
    TI__Guru* 91947 points

    John,

    We are looking into this.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Mastermind 44680 points
    Hi John
    The recommended flight rated clocking device consists of the CDCM7005-SP along with an appropriate VCO or VCXO.
    LVPECL mode outputs should be used, with 150 ohm terminations to ground (see Figure 16 of the CDCM7005-SP datasheet).
    The differential signal should then be AC coupled to the ADC CLK+/- inputs which have built-in DC biasing and termination. The 83-ohm/130-ohm terminations shown in Figure 26 are not needed for this ADC.
    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    Prodigy 180 points

    Hi Jim, 

    Thanks for the response. We have used this solution in the past for other flight applications and are comfortable with this circuit.

    For this particular ADC application, we have found through lab testing and through the published TI app notes that the ADC spectrum is very sensitive to harmonics on the input sample clock. We have a wide band application and need to be cognizant of any fixed frequency spurs due to the sample clock. One way to mitigate this is to provide a band pass filter for the sample clock to knock down harmonics. I would tend to think that this is not recommended when using a jitter cleaner solution, such as the CDCM7005-SP given that we want a fast edge to minimize aperture jitter. A band pass filter would essentially slow the clock edge down and make it more sinusoidal.

    Here in lies the trade off; is it better to use a jitter cleaner with a fast clock edge at the expense of introducing fixed frequency spurs? Or is it better to use a clean sinusoidal input with appropriate filtering at the expense of increasing aperture jitter? 

    I'm sure there are other considerations here. I would appreciate any other inputs or thoughts TI might have here. 

    Reference TI app note: Plisch, Marjorie, “Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigation”, Texas Instruments, SLAA617, December 2013.

    Regards,

    John

  • 0 in reply to John Roy94
    TI__Mastermind 44680 points

    Hi John

    We have achieved good results in commercial applications using other jitter cleaner type devices with LVPECL type outputs to clock similar ADCs. The high slew rate non-sinusoidal clock signals do not cause a problem with ADC performance.

    It is always important to ensure there is no coupling from any clock signals to power, ground or analog input signals to maintain good performance.

    Best regards,

    Jim B