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ADS8860: ADS8860: ADS8860 / ADS8861 Not releasing SDO on power-up

Chris Ponder
Prodigy 120 points
Part Number: ADS8860
Other Parts Discussed in Thread: ADS8861

I posted about this in September and Evan Sawyer kindly responed:

https://e2e.ti.com/support/data_converters/precision_data_converters/f/73/t/625978

I am now in a position to add the additional information requested, but the thread is locked and I can see no way to request that it be unlocked. So, I am continuing here, please feel free to move this to the original thread.

So I have finally got working boards and time to investigate this further. The boards have had the AVDD supply set to 3.3V and have had the ADC ICs replaced with new parts. The problem is still occuring with all three ADCs needing to be run through one conversion before they will release the SDO line The SPI signal lines on power-up look like this:

The supplies on power-up are:

The 6V is simply the system supply, AVDD and DVDD are the ADC supplies.

With the VREF supply this is:

VREF looks way too slow to me, but I have another reference laid out which works better:

Again this made no difference, SDO is still stubbornly stuck low on power-up


Any help would be much appreciated.

  • 0
    TI__Mastermind 21685 points
    Chris,
    We will review and come back to you on this.
    Thanks,
    Vishy
  • 0 in reply to Chris Ponder
    Prodigy 120 points
    Hi, is there any progress on this?
    Thanks
  • 0 in reply to Chris Ponder
    TI__Intellectual 1205 points
    Chris:

    In the ADS8860 datasheet, p. 25, it mentions that DOUT will be driven low when DIN and CONVST are low together. On power-up, this seems pretty likely to happen. Is this what is going on in your circuit? Are your units daisy-chained together, or do you have separate SPI interfaces?

    --Bryan
  • 0 in reply to Bryan McKay
    Prodigy 120 points

    Hi Brian,

    The devices share a single SPI bus and are controlled by nCS (DIN), which why there is a problem as they share the DOUT line. DIN & DOUT are both pulled high with a 10k resistor while ConvST is pulled low. In theory, these lines should be pulled to the correct values on power-up, but I could try a stronger pull up.

    Thanks

    Chris

  • 0 in reply to Chris Ponder
    TI__Intellectual 1205 points
    Chris:

    I think you really want to use 4-wire nCS mode, without a BUSY indicator. Your description of your system sounds like Figure 54, p. 23 of the datasheet for the ADS8860.

    In reading back through your conversation, it looks like you originally started out with the 4-wire mode, but with the BUSY indicator on. The BUSY indicator drives the SDO low to indicate a conversion is complete until the data has been read, so it looks like you want to disable the BUSY output.

    DIN being high on the rising edge of CONVST puts the device into nCS mode. Driving DIN low after the end of the conversion and reading the data with CONVST still high keeps the device in 4-wire mode. (Driving DIN low before the conversion is complete enables the BUSY indicator.)

    From the datasheets, it looks like the ADS8860 and ADS8861 should both power up in acquisition mode, which means effectively powered down, with DOUT in high impedance state. My guess is that the power-up sequence in your system is somehow triggering one conversion, and causing DOUT to be driven low to indicate that a conversion is complete because the BUSY indicator is enabled. However, the scope shots that you sent look OK to me. Maybe your devices are seeing a glitch that is not being caught by the scope? Note that if CONVST goes high while DIN is low, then the device thinks you want to be in daisy-chain mode, and DOUT will be driven low.

    --Bryan
  • 0 in reply to Bryan McKay
    TI__Intellectual 1205 points
    Chris:

    One other suggestion is that you replace the pullup on the DIN lines with zero-ohms. If the unit powers up with the DIN pin in a logic low state, it sends the interface to the Daisy-Chain mode, where SDO pin drives low. Even then, starting a conversion should bring the SDO pin to high-impedance state if DIN is high at that time. If DIN is not high at the rising edge of CONVST, the device will continue to drive the SDO low through the conversion.