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ADS52J90EVM: TX_TRIG Questions

Li Zhang71
Prodigy 90 points
Part Number: ADS52J90EVM
Other Parts Discussed in Thread: ADS52J90, LMK04826

Hello there,

Let me first explain my problem: 

I have a design with ads52j90 configured for 32 Channel mode, 50M sample per second , using 8lanes jesd interface with xilinx kcu105.  I connected two analog signals to channel 1 and channel 23.  Both channel1 and channel23 are SMA connector that faces up. I can see both signals on the fpga side using logic probe.  However, the problem is that signal 1 and signal 2 does not always fall under the same odd/even frame.  

Below is a case when signals fall under different odd even group.

Below is a case when signals fall under the same odd even group.

The datasheet mentioned that TX_TRIG signal acts as a reference for odd-and even channel sampling instant.  

What is the period TX_TRIG signal?

The TX_TRIG signal should be asserted before or after JESD interface phases?  

Please let me know if I'm missing something or it is not a TX_TRIG problem entirely.  Thanks.

Li 

  • 0
    TI__Expert 4145 points

    Hi Li,

    The main reason you are seeing this issue is because the device expects SYSREF to be used to synchronize its odd and even channels when using JESD.

    Edit: The TX_TRIG signal doesn't reset the JESD block of the IC so the SYSREF is recommended instead (can be programmed to reset both the JESD block and device PLLs).

    The next revision of the datasheet will detail this further.

    Sincerely,

    Olu

  • 0 in reply to Olu Sodipe
    Prodigy 90 points

    Hi Olu,

    Thank you for pointing me in the right direction.

    I'm using periodical sysref and I only want the first sysref event to take effect. Just want to confirm that the following
    is the correct setting for using sysref event to reset both the jesd and device pll.

    JESD_RESET1 in register 0x46 set to 0
    JESD_RESET2 in register 0x4A set to 0
    JESD_RESET3 in register 0x4A set to 1

    edit: I tried with this setting but sometimes the two signals still falls in two different odd even phase.



    Best Regards,
    Li

  • 0 in reply to Li Zhang71
    TI__Expert 4145 points

    Hi Li,

    So there are two key points--the transmission of 32 ADC samples (for 32 channels) using a 16 channel JESD interface and aligning the even/odd channels.

    • In 8-Lane mode with 2 ADCs per lane, the ADS52J90 transfers all 32 channels in 16 channel frames--when JESD TX block is aligned properly, an even data frame comes first before being followed by an odd frame.
      • For example after the LMFC boundary, lane 1 will have channel 2 followed by channel 4 as one frame before channel 1, channel 3  in the next frame.
      • This means your multiframe needs to be large enough to contain both frames.

    • To align the even/hold channels, the key is to have SYSREF reset both the  device PLLs and JESD block by running the following sequence after JESD link configuration (no signal at TX_TRIG pin).

      • Set JESD_RESET1, JESD_RESET2 and JESD_RESET3 to 0x00.
      • Turn on continuous SYSREF to ensure all device blocks are reset.
      • Channels should now be aligned with even channel first after the LMFC boundary--you can now turn off continuous SYSREF and configure JESD_RESETx as needed for your application.

    Sincerely,

    Olu

  • 0 in reply to Olu Sodipe
    Prodigy 90 points

    Hello Olu,

    Thanks again for the help.  My multiframe number K is set to 16 (0x53 = 0x000f) with FORCE_K = 1.

    I followed the following steps with (TX_TRIG off):  

    1. Set JESD_RESET1, JESD_RESET2 and JESD_RESET3 to 0x00.

    2. Turn on continuous SYSREF to ensure all device blocks are reset.

    3. Channels should now be aligned with even channel first after the LMFC boundary--you can now turn off continuous SYSREF and configure JESD_RESETx as needed for your application.

    Apply these three steps did not solve the problem but it leads me to suspect that there might be some problem with my SYSREF signals.  

    There is an example for setup SYSREF in LMK0482xB data sheet --> 9.3.2.1 How To Enable SYSREF section --> 9.3.2.1.1 Setup of SYSREF Example.  

    I followed this example to set up the LMK04826 SYSREF generation as pulse mode and then applied the three steps. 

    Finally, the odd-even frames for all channels are aligned every time during power up.  

    Best Regards,

    Li