• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 486 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1271 short circuit noise

Calum Mackinnon
Genius 4155 points
Other Parts Discussed in Thread: ADS1271

ADS21While evaluating the ADS1271 shorted-input noise I encountered very significant 3 to 4 Hz periodic noise. The shorted input noise is about 240 counts peak-to-peak (Standard deviation = 40 ) and the periodic noise appears to be around 130 counts peak-to-peak. Is this 3-4 Hz periodic noise a known behavior of the ADS1271? Are there sampling rates or modes that can reduce it? Thank you

  • 0
    TI__Mastermind 43915 points

    Hi Calum, 

    Depending on the mode that you are running the ADS1271 in, the noise will differentiate. In the worst case, High-speed mode, the noise is specified (with shorted inputs) as 16uVrms max. Converting this to peak to peak noise, you will see it is about 105uV peak to peak (16uVrms * 6.6). Now in your ADS1271, I am going to assume you are using a 5.0V reference. If this is the case, your LSB size will be 298nV. Therefore your peak to peak noise in LSBs is roughly 350 codes worst case (105uV/0.298uV). If you are using a smaller reference, you can expect the noise to be a larger amount of codes. So from the peak to peak noise, it does not look like you are seeing something unexpected. 

    Now, with the ADS1271, there are things you can do to increase the performance and reduce the noise. For example, we have seen the noise performance increase when the SCLK and master clock are multiples of one another and in phase. If the SCLK is 1/4 the frequency of the master clock you will notice less noise than if they are out of phase. Note, that when they are not in phase, the ADC's noise will still be in spec, just not optimized. You can also look into making sure you have clean supplies power supplies and that you are shorting the two input pins together directly at the device. 

    Regards,

    Tony Calabria 

  • 0 in reply to Tony Calabria
    Genius 4155 points

    Tony,

    Thank you very much for the information.  Unfortunately, it did not address the question.

    1)  I computed the standard deviation of the noise as 40 ADC counts.  Taking this as the rms noise value, the SNR is 20 * log( 2^24 / 40 ) = 112 dB, which is well within specifications and is NOT in question.

    2)  What IS in question is the substantial periodic component of the noise, on the order of 3-4 Hz.  I sent a reasonably complete .pdf document describing this periodic noise along with the question.  I have attached a copy to this Email to help our understanding of the real problem.

    Thank you,

    Calum

    ADS1271drift.pdf
  • 0 in reply to Calum Mackinnon
    TI__Mastermind 43915 points

    Hi Calum, 

    Thank you for your clarification. At a 24-bit level you are going to see noise from a variety of sources; power supplies, reference voltage, environmental changes such as the air conditioner turning on, ground plane, etc. At this level, you are going to need to make sure that your layout is correct with large caps on the supply and reference lines placed physically as close to the ADC pins as possible. You are also going to want to make sure that the board is tested in an isolated climate such as in a static bag avoiding interference from anything external. 

    Regards, 

    Tony 

     

     

  • 0 in reply to Tony Calabria
    Genius 4155 points

    Hi Tony,

    This is for a customer of mine.

    I think he is really asking if the noise he is seeing is a function of the device? Reading througfh his document he has tried to eliminate all external sources of noise by shorting the inputs to his supply volatge, granted there are other sources but he has tried. Is there an evaluation module that he or you can experiment on to see if similar results are seen?

    Cheers

    Calum

  • 0 in reply to Calum Mackinnon
    TI__Mastermind 43915 points

    Calum, 

    The ADS1271 device as itself under ideal conditions (clean, in sync clocks, transient free input voltages, etc.) , does not exhibit any known behavior as your customer has explained. However, as explained previously, what your customer is seeing as far as the noise behavior is concerned looks very similar to what we see in some of our EVM testing. Unless your test setup is isolated with clean, synced signals and very steady power supplies, you can expect some environmental impact to the system. We have noticed changes to results on the 24 and 32 bit levels by simply placing the test setup in an anti-static bag. Additionally, I met with the design group to get their idea on this and they believed that one possible reason could be if the master clock and SCLK are slightly out of phase at all, it could cause some small 3-4Hz behavior. 

    Regards,

    Tony