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Hi Team，
I am looking for one kind of DAC,which can help me achieve the following aims:
DAC clock rate:200M ,and the input data rate is 400M ，with the I Q sequence interleaved.so that I can latch the I data in the rising edge of clk and latch the Q data in the following falling edge of input clk.
just like the following picture：
I wonder whether DAC5672 can realize the goal ，if I use the mode of single-bus interleaved mode.
If not ,I wonder appreciate it if you can tell which DAC chip can exact realize my designing goals;
Thanks for replying.However I still have some problems.Single-Bus Interleaved Mode Operation drawn from datasheet is shown as below.
In the figure,the Select IQ rate is half the CLK. In my projects,I need to latch the I data in the rising edge of clk and latch the Q data in the following falling edge of input clk. It means the Select IQ rate should be the same as the input clock. whether it's practicable keep Select IQ rate the same as input clock.
another question is from the datasheet,it tells".The edge-triggered flip-flops latch the A- and B-channel input words on the rising edge of the write input (WRTIQ). This data is presented to the Aand B-DAC latches on the following falling edge of the write inputs. The DAC5672A clock input is divided by a factor of two before it is presented to the DAC latches". Both A and B DAC latch input data on the falling edge of write input, How can it achieve my designing goal.
