• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 48 subscribers
  • Views 771 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12J4000EVM: ADC12J4000EVM Test Pattern mode – Data Alignment

Shai Gilboa
Prodigy 60 points
Part Number: ADC12J4000EVM
Other Parts Discussed in Thread: ADC12J4000,

We are evaluating the ADC12J4000 ADC using both the ADC12J4000EVM and the TSW14J56EVM.
Test Pattern mode is selected in the ADC12J4000EVM, and ADC12J4000_Bypass is selected on the TSW14J56EVM.
The content of JESD204B lanes and other information are captured (ALTERA SignalTap), and then compared with expected Test Pattern values (Table 33 in the datasheet).
Captured data does not seem to be aligned, as the location of the trailing 4-bit zeros (red colored) is not fixed. Example follows.

SignalTap signals:
jesd204b:jesd204b_inst|jesd_top_qsys:jesd_top_qsys_0|jesd_top:u_jesd_top_inst|jesd_rx_top:JESD_RX.u_jesd_top_rx|serdes_data_in_r1[7][31..0]
jesd204b:jesd204b_inst|jesd_top_qsys:jesd_top_qsys_0|jesd_top:u_jesd_top_inst|jesd_rx_top:JESD_RX.u_jesd_top_rx|serdes_data_in_r1[6][31..0]
jesd204b:jesd204b_inst|jesd_top_qsys:jesd_top_qsys_0|jesd_top:u_jesd_top_inst|jesd_rx_top:JESD_RX.u_jesd_top_rx|serdes_data_in_r1[5][31..0]
jesd204b:jesd204b_inst|jesd_top_qsys:jesd_top_qsys_0|jesd_top:u_jesd_top_inst|jesd_rx_top:JESD_RX.u_jesd_top_rx|serdes_data_in_r1[4][31..0]
jesd204b:jesd204b_inst|jesd_top_qsys:jesd_top_qsys_0|jesd_top:u_jesd_top_inst|jesd_rx_top:JESD_RX.u_jesd_top_rx|serdes_data_in_r1[3][31..0]
jesd204b:jesd204b_inst|jesd_top_qsys:jesd_top_qsys_0|jesd_top:u_jesd_top_inst|jesd_rx_top:JESD_RX.u_jesd_top_rx|serdes_data_in_r1[2][31..0]
jesd204b:jesd204b_inst|jesd_top_qsys:jesd_top_qsys_0|jesd_top:u_jesd_top_inst|jesd_rx_top:JESD_RX.u_jesd_top_rx|serdes_data_in_r1[1][31..0]
jesd204b:jesd204b_inst|jesd_top_qsys:jesd_top_qsys_0|jesd_top:u_jesd_top_inst|jesd_rx_top:JESD_RX.u_jesd_top_rx|serdes_data_in_r1[0][31..0]

Capture #1:

Lanes
7 6 5 4 3 2 1 0
FF0B40FFh FF0D20FFh 00F1EF00h FB40F0FBh FD20F0FDh 01F0FE10h 70FF0870h FF0F00FFh
F4BF0040h F2DF0020h EF00F1EFh F0FB40F0h F0FD20F0h 0F01EF0Fh 0070FF08h F0FF0000h
00F4BF00h 00F2DF00h FF0E10F0h 04BF0F04h 02DF0F02h FE0001EFh 8F00F78Fh 00F0FF00h
0B40F0BFh 0D20F0DFh 10FF0E10h 0004BF0Fh 0002DF0Fh F0FE10F0h FF8000F7h 0F00F0FFh


 Data Ordering #1:

C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Lane 0 FF 00 0F FF 00 00 FF F0 00 FF F0 00 FF F0 00 0F
Lane 1 70 08 FF 70 08 FF 70 00 8F F7 00 8F F7 00 80 FF
Lane 2 10 FE F0 01 0F EF 01 0F EF 01 00 FE F0 10 FE F0
Lane 3 FD F0 20 FD F0 20 FD F0 02 0F DF 02 0F DF 02 00
Lane 4 FB F0 40 FB F0 40 FB F0 04 0F BF 04 0F BF 04 00
Lane 5 00 FE F1 00 EF F1 00 EF F0 10 0E FF 10 0E FF 10
Lane 6 FF 20 0D FF 20 00 DF F2 00 DF F2 00 DF F0 20 0D
Lane 7 FF 40 0B FF 40 00 BF F4 00 BF F4 00 BF F0 40 0B

 

Capture #2:

Lanes
7 6 5 4 3 2 1 0
FF0B40F0h 20F0DF00h FF0E10F0h 04F0FB40h 02DF0F02h F0FE10F0h FF0870FFh 00FF0F00h
40FF0B40h 0D20FF0Dh 10FF0E10h 0F04BF0Fh 0002DF0Fh 01EF0F01h F78F0070h 0000FF0Fh
00F4BF00h DF0020FFh 00F1EF00h FB0004BFh FD20F0FDh 0001EF0Fh 00F78F00h FF00F0FFh
BF00F4BFh F2DF00F2h EF00F1EFh F0FB40F0h F0FD20F0h FE10F0FEh 0870FF80h F0FF00F0h

Data Ordering #2:

C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Lane 0 00 0F FF 00 0F FF 00 00 FF F0 00 FF F0 00 FF F0
Lane 1 FF 70 08 FF 70 00 8F F7 00 8F F7 00 80 FF 70 08
Lane 2 F0 10 FE F0 01 0F EF 01 0F FE 01 00 FE F0 10 FE
Lane 3 02 0F DF 02 0F DF 02 00 FD F0 20 FD F0 20 FD F0
Lane 4 40 FB F0 04 0F BF 04 0F BF 04 00 FB F0 40 FB F0
Lane 5 F0 10 0E FF 10 0E FF 10 00 EF F1 00 EF F1 00 FE
Lane 6 00 DF F0 20 0D FF 20 0D FF 20 00 DF F2 00 DF F2
Lane 7 F0 40 0B FF 40 0B FF 40 00 BF F4 00 BF F4 00 BF

Please advise regarding the issue described above.

Regards,

  • 0
    TI__Genius 12780 points

    Hi Shai,

    We are taking a look into your question, and will be back with you soon.

    Best Regards,

    Dan

  • 0 in reply to dBrock
    TI__Mastermind 44680 points

    Hello Shai

    I apologize that no-one has responded to address your question before now. Are you still trying to resolve the information seen in Signal Tap?

    I do not have the FPGA inspection tools available, but I know that after the JESD204B completes the ILA sequence that the data is consistently aligned. Since the HSDC Pro data capture is aligned to the start of multi-frame, the data pattern is always in exactly the same position for each capture.

    Here is a snapshot of the HSDC Pro output of the ADC Test Pattern Mode Data in Codes View:

    And here is Bits View:

    And here are the first 80 samples (the pattern repeats every 2 frames of data which is 80 samples):

    Samples - Waveform

    ADC Codes - Waveform

    0

    0

    1

    8

    2

    16

    3

    32

    4

    64

    5

    256

    6

    512

    7

    1024

    8

    4095

    9

    4087

    10

    4079

    11

    4063

    12

    4031

    13

    3839

    14

    3583

    15

    3071

    16

    0

    17

    8

    18

    16

    19

    32

    20

    64

    21

    256

    22

    512

    23

    1024

    24

    4095

    25

    4087

    26

    4079

    27

    4063

    28

    4031

    29

    3839

    30

    3583

    31

    3071

    32

    0

    33

    8

    34

    16

    35

    32

    36

    64

    37

    256

    38

    512

    39

    1024

    40

    4095

    41

    4087

    42

    4079

    43

    4063

    44

    4031

    45

    3839

    46

    3583

    47

    3071

    48

    0

    49

    8

    50

    16

    51

    32

    52

    64

    53

    256

    54

    512

    55

    1024

    56

    4095

    57

    4087

    58

    4079

    59

    4063

    60

    4031

    61

    3839

    62

    3583

    63

    3071

    64

    0

    65

    8

    66

    16

    67

    32

    68

    64

    69

    256

    70

    512

    71

    1024

    72

    4095

    73

    4087

    74

    4079

    75

    4063

    76

    4031

    77

    3839

    78

    3583

    79

    3071

     Is the capture point is signal tap after the JESD204B IP has aligned the lanes together using the elastic buffer release mechanism?

    If so the data from all lanes should be aligned.

    Best regards,

    Jim B