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DAC38RF82: No CLKTX+/- signal

Gil Hershman71
Intellectual 580 points
Part Number: DAC38RF82

Hi,

We are unable to see any signal on CLKTX+/- pins (a divided DAC CLK).

We only see a DC level of 750mV on both pins.

  • We use the DACCLKSE input (9GHz / 1Vpp sine wave via DC block capacitor), bypassing the DAC PLL.
  • We followed the sequence in figure 141 (DAC38RF82/89 Recommended Startup Sequence) until the "On chip PLL mode".
  • The following registers were configured:
    CLK_PLL_CFG = 0x2200
    CLK_OUT = 0x0802
    SLEEP_CONFIG = 0x0020
  • In addition, the following registers values are:
    RESET_CONFIG = 0x5803
    VENDOR_VER = 0x8009
  • We bypassed the steps in figure 141 from "On chip PLL mode" and until "Stop SYSREF generation..." (including).
  • Pulled TXENABLE high.

What are we missing here, that causes not seeing anything on CLKTX+/- pins ?

Thanks,

Gil

  • 0
    TI__Genius 12780 points
    Hi Gil,

    Your question is being reviewed, and we will be back with you soon.

    Best Regards,

    Dan
  • 0 in reply to dBrock
    TI__Guru* 91947 points

    Gil,

    After power is applied and the single-ended clock is provided, toggle the external reset pin low then back high. Write the following data to the following registers:

    Address     Data

    0x040C     0xA002

    0x40B        0x0022

    0x431        0x3000

    See if this provides an output that is a divide by 4 of the input clock.

    Regards,

    Jim 

  • 0 in reply to jim s
    Intellectual 580 points

    hello Jim,

    I suspect we have instabilities in the SPI read and write transactions.

    1. I assume, as stated in figure 141, that before being able to read any register, we need to perform the following:
      TXENABLE=low, TRSTB=low, supply external DACCLK, define SEL_EXTCLK_DIFFSE (since we use the DACCLKSE pin),  RESETB toggle, check for 0x7F[15:10]=10000b.
      Am I correct here?
    2. How meaningful is it to have TXENABLE=low before applying the supply rails?
      We are pulling it low by our FPGA after the supply rails are stable.
    3. We performed the steps in (1) above.
      We face instabilities in reading DAC registers.
      Every read (from 0x7F for example) returns a different value. Sometimes it's the correct 0x8009, but other times it is other values.
      I am not sure whether these are SPI-bus issues (all seems ok, timing and voltage wise) or DAC configuration issues

    Regarding the above registers you asked to write, I want to verify:

    These registers are on page_set 4.
    CLK_TX_IDLE=1
    CLK_TX_SLEEP=1
    Please confirm.

    I am preparing what you asked and will hopefully reply shortly.


    In the meantime, I will much appreciate you reply for my above remarks.

    thanks

    Gil

  • 0 in reply to Gil Hershman71
    Intellectual 580 points
    hello Jim,

    Configuring the above, as requested:
    No signal on CLKTX+/- pins (only a 1V DC on both pins).

    I also tried it with
    CLK_TX_IDLE=0
    CLK_TX_SLEEP=0

    and no signal.

    thanks
    Gil
  • 0 in reply to Gil Hershman71
    TI__Guru* 91947 points

    Gil,

    On our customer EVM, I would provide a clock, power up the board, do a hard rest, then load the registers with the default settings. After taking the CLKTX out of the default sleep and idle modes, I would get an output clock. The full register settings are attached for your reference.

    Regards,

    Jim

     CLKTXP_register_settings.cfg

  • 0 in reply to Gil Hershman71
    TI__Guru* 91947 points

    Gil,

    You are correct for #1. TXENABLE is just a safety feature and has nothing to do with the SPI interface.

    For #2, it does not matter. This just forces the DAC output to mid-scale if you have it set low. If not set low, the DAC output is unknown which could cause a problem downstream if you were driving a PA.

    For #3, are you using 3 wire or 4 wire mode? Is you SPI bus shared with other devices? Are you running the SPI clock to fast?

    If you want to use CLKTX output, both CLK_TX_IDLE and CLK_TX_SLEEP bits need to be set to "0".

    Regards,

    Jim