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ADS1248: issues regarding ADS1248

Yash Dave
Intellectual 620 points
Part Number: ADS1248


Hi,

The brief of our design with ADS1248 IC is as follows :

  1. ADS1248 is used in Bi-polar mode (+/- 2.5V) with internal reference (2.048V) used.
  2. Analog input is differential input & ADS1248 channel used is AIN6 & AIN7 for the same.
  3. Analog voltage input range is 0 to 10V and -10V to +10V.
  4. We are giving user analog input voltage at Point V+ and V-. At point A &B, we are getting  x0.09 attenuated voltage and same goes to ADS1248 IC channel AIN6 & AIN7.  e.g. for 10V analog input at V+ & V-, we are getting approx. 0.9V at ADS1248 IC channel AIN6 & AIN7.
  5. PGA gain used is 1 

During testing,  we found following observations with PGA gain 1:

  1. When voltage at ADC1248 IC  differential input pin (AIN6 / AIN7) is below 1.02V, we are getting linearly increasing 24bit Raw data.

i.e. for 0V to 12.5V analog input at V+ and V- , we are getting apporx. 0V to 1.028V at ADS1248 IC channel AIN6 & AIN7. For this ADS1248 raw data is 1965 to  4411158 (Decimal)

  1. However when voltage at ADS1248 IC channel AIN6 & AIN7 goes above 1.02V, ADS1248 raw data starts to decrease exponentially

                i.e. for 12.6V to 26V analog input at V+ and V-, we are getting apporx. 1.028V to 1.85V at ADS1248 IC channel AIN6 & AIN7. For this ADS1248 raw data is    

               4241086 to  2218621 (Decimal)

 

During testing,  we found following observations with PGA gain 2:

  1. When voltage at ADC1248 IC  differential input pin (AIN6 / AIN7) is below 1.02V, we are getting linearly increasing  24bit Raw data.

i.e. for 0V to 12V analog input at V+ and V-, we are getting apporx. 0 to 1.024V at ADS1248 IC channel AIN6 & AIN7. For this ADS1248 raw data is 455 to  8085651 (Decimal)

  1. However when voltage at ADS1248 IC channel AIN6 & AIN7 goes above 1.02V, ADS1248 raw data starts to decrease exponentially

                i.e. for 13V to 26V analog input at V+ and V-, we are getting apporx. 1.107V  to 1.85V at ADS1248 IC channel AIN6 & AIN7. For this ADS1248 raw data is   

               6949233 to  3048501 (Decimal)

 

From above two readings, we found that when voltage at ADS1248 IC differential input channel (AIN6 & AIN7) is  above approx.1.028V, then 24bit Raw data start to decrease as voltage increases, which should not happen.

 

Our query is, why ADS1248 IC, 24 bit raw data starts decreasing (above 1.028V) when its differential input channel AIN6 & AIN7 voltage increases even though this voltage is below internal reference voltage.

 

Pls. let us know, how we should proceed to resolve this issue?  

  • 0
    TI__Guru* 98785 points
    Yash,


    I'm not sure what the problem is with the circuit. If the input voltage over-ranges the full-scale range of the ADC, the ADC output data should be clipped to the output full scale of 7FFFFFh for the reading.

    To help debug this, I'll need some more information about your setup and the operation of the ADC. I'd like to see a schematic of the circuit, including the input sources, input filtering and all the connections to the device. Because your inputs extend all the way to -10V to +10V at the maximum, you do require some input scaling. Do you use a simple resistive voltage divider? If so, what values are you using (or just show it on the schematic). If the input is some sort of buffer amplifier, show that too.

    I'd also like to know all of the register settings for the device. What is the data rate? Are IDAC currents, VBIAS voltages, or burnout current sources enabled? These settings may affect the measurement. Also, are the FCR and OCR values calibrated or written to? These may affect the output data as well.

    Just to make sure that you have the inputs are within the operating range of the PGA (even if the PGA gain is 1), is AIN6 always at 0V? and are the voltages at AIN7 the voltages reported in the post? To be clear you may want to report the voltages of both AIN6 and AIN7 with respect to ground for each input. As you change to a PGA gain of 2, you are almost definitely violating the common-mode input range as described on page 27 of the datasheet.

    How do you have the VREFCOM connected? Have you verified that the reference voltage is enabled by measuring the voltage from VREFCOM to VREFOUT?

    Just to be sure, I would make make measurements of all the relevant voltages on the circuit. Makes sure that AVDD=2.5V, AVSS=-2.5V and that all the other voltages (AIN6, AIN7, VREFOUT, VREFCOM, DVDD, DGND) are all correct.

    Again I'm not sure what the problem is in this circuit. I might also suggest making several measurements of different input voltages (perhaps going from 0.1V, 0.2V, 0.3V, going up to 2.0V) and recording the output data so you know exactly how the output data changes with the input voltage. This might be a bit complicated, but might help narrow down the problem.


    Joseph Wu
  • 0 in reply to Joseph Wu
    Intellectual 620 points
    can you share your mail id to send schematic?
  • 0 in reply to Yash Dave
    TI__Guru* 98785 points
    Yash,


    In the upper right hand corner of the e2e page, you'll find a notice where I've "requested friendship". Accept this, and you'll be able to send me the schematic privately so that it's not visible to everyone on e2e. After accepting the friendship, use the message notices button also on the upper right hand corner of the page. This will lead you to a link to write a new message.


    Joseph Wu
  • 0 in reply to Joseph Wu
    TI__Guru* 98785 points
    Yash,


    I've sent you a message. As in the previous post, you should be able to click in the message box in the upper right hand corner of the e2e page after you've logged in. I'll wait for you to send the schematic through the message system.


    Joseph Wu
  • 0 in reply to Joseph Wu
    TI__Guru* 98785 points
    Yash,


    I've reviewed your schematic and sent you back some comments through the message system. Have you had a chance to review them and make any changes? I wanted to make sure that the comments helped.

    The main problem was the voltage divider in used in front of the ADC. The way it was constructed, it violates the common-mode input range of the PGA. By making a small change to the divider and referencing the divider to ground, it still performs the voltage division and keeps the input voltage within the PGA input range.

    If this helped, great. I'll close out the post soon. If it didn't or if you have further questions, you can post back to this thread or send me another message. If the post is closed, then you can start another post.


    Joseph Wu