DAC7760: HTSSOP-24

Marceli Firlej

Prodigy 50 points

Part Number: DAC7760

Does LATCH toggle sequence can be done after data transmission without CLK clock synchronisation?

over 7 years ago

0 Matthew Sauceda over 7 years ago

TI__Genius 11750 points

Howdy Marceli,

This is shown in Figure 1 of page 12 of the DS. Latch can be brought low when clocking in contents and pulled high to latch in the data after 24 clock cycles. Please let me know if this answers your question.

Best Regards,

Matt

0 Marceli Firlej over 7 years ago in reply to Matthew Sauceda

Prodigy 50 points

Hi Matt,

In mine generated NXP's SPI driver by Processor Express is difficult do it when clock is clocking. Can LATCH be toggle high to low without clock after clocking has finish operation? Does latch need use clock?

Regards,

0 Matthew Sauceda over 7 years ago in reply to Marceli Firlej

TI__Genius 11750 points

Howdy Marceli,

You can toggle or pulse the Latch pin from LOW-HIGH-LOW after data is written. You do not need to use synchronize SCLK during the LATCH operation.

Best Regards
Matt

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DAC7760: HTSSOP-24