HI,
There are two JESD204B Links in ADC12DJ3200. When using the ADC's JMODE 0, can I generate a 8 lanes JESD204B IP core with Xilinx FPGA ?
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HI,
There are two JESD204B Links in ADC12DJ3200. When using the ADC's JMODE 0, can I generate a 8 lanes JESD204B IP core with Xilinx FPGA ?