Hello support team,
I have questions about DAC5672.
Please teach me about the clock timing in case sending data in dual-bus mode.
There is following description in section 7.3.2 "Dual-Bus Data Interface and Timing" on page 15 of datasheet.
"The rising edge of CLKA, CLKB must occur at the same time or before the rising edge of the WRTA, WRTB signal. "
How much tolerance is there between the rising edge of CLK and it of WRT in case that CLK and WRT rise at the same time?
The signals of CLK and WRT will be supplied from output of CDCLVC11xx.
CDCLVC11xx has skew of about 50 ps between channels.
Considering the wiring length of signal on board, I think that the skew further increases.
I am concerned about supplying CLK and WRT from CDCLVC 11xx.
Is there any problem?
Best regards,
M. Tachibana
