DAC38J84EVM: SPI interface

Hi Mallesh,

We are taking a look into your query, and will be back with you soon.

Best Regards,

Dan

Hello Dan,

I did figure that out. FMC_B5 and FMC_B6 are connected to dac_SDIO and LMK_SDIO respectively. I am able to read and write to both the devices. 

Now, I have more questions regarding initialization. 

1. DAC reset: You have DAC_reset signal connected to RESETB of the dac38J84. How do I drive this signal from FMC?

                       Also, Is there  any other dac reset register?

2. In dac initialization step 1 says "Set TXENABLE low". How do I do this?

3. After clock initialization and dac initialization, I initialize FPGA jesd interface. After this, I need to do following steps on GUI.

     a. Reset DAC core. 

     b. Trigger LMK04828 SYSREF

    Which registers should be written to provide the functionality of the above steps. 

Thanks and Regards,

Mallesh

   

Jim,

FMC_B5 and FMC_B6 are connected to dac_SDIO and LMK_SDIO respectively. So I can not use them for resetting DAC.

Is there any other signal that can be used for resetting DAC?

Mallesh

Mallesh,

If you have a spare SMA on the FPGA board, in your firmware, assign the SYNC to this then cable across to the header on the DAC board. We have done this before with an Altera development board.

Regards,

Jim

Mallesh,

In my last post, I meant to say DAC_RST, not SYNC. There should be plenty of spares on either J24 or J25 you can connect this cable to from the FPGA board. You then will have to modify the CPLD firmware.

Regards,

Jim

Jim,

Thank you. I should be able to do that. Please send me the current project files. I will just modify it and use it.

Thanks again.

Mallesh

Jim,

Can you please send me the CPLD files for TSW38J84 EVM board also?

Thanks,

Mallesh