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ADS1298: positive-end saturation

Part Number: ADS1298

Hi,

I set  VREFN to the ground  and connect to AVSS, and I measure the VREFP as 2.4V.

At meantime, I set PGA as 6.

I think the full-scale voltage  is supposed to be +-400mV.

But when I feed a 10Hz 700mV p-v sin waveform it saturated about 240mV at positive end.

  • Hi Harvey,

    You are correct in that the FSR is 400 mV. One thing that would be causing the signal to clip in the positive peaks is that your common mode voltage is too high. Please look at page 32 in the datasheet where it talks about the Input Common-Mode Range. If you use a Vcm within the range you should see the whole signal with no clipping. 1.25 V < CM < 1.75 V.
  • Hi Matt,

    At beginning, I set the register 0x0D as 0x00, register 0x0E as 0xFF, and the waveform saturated.

    After, I set the register 0x0D as 0xFF, register 0x0E as 0xFF, and the waveform can be read correctly.

    Why set register 0x0D as 0x00 didn't work.

    The negative end of 8 channels are connected together.

  • Hi Harvey, 

    The 0x0D and 0x0E registers are the RLD Positive Signal Derivation and RLD Negative Signal Derivation registers respectively. When you have both on, you are enabling the RLD DC Bias Circuit on the positive and negative. On page 41 it talks about this. When you have only the Negative signal bias enabled, the part is able to offset any negative common mode drift thus why you're seeing a good reading in the negative region. But when you have the positive channel disabled, it is possible that the common mode voltage is drifting upward. I would suggest enabling both and seeing if that fixes your issue. Also page 86 discusses establishing a common mode voltage and why you need a negative feedback.

    P.S. What is your Vcm, as per my first suggestion? That could also be a part of the problem if it is too high.