DAC38RF82EVM: DAC38RF82EVM JESD204 error

My error:

Are you able to get the link operational when using a standard 5898.24 clock? I am wondering if the LMK clock and dividers are not optimized properly FPGA with the 6144 MHz clock.

You can also check/verify that you select the JESD reset once the pattern is sent to ensure the link is reset and active.

--RJH

Thank you so much for your support Rusell,

I changed the parameters of my demo following your suggestion: DAC lock frequency 5898.24MHz. But I got the same error with JESD204. Beside that, I checked reset state was done with K28.5 characters in transmitter. The problem shown more detail below:

DAC configurations:

TX status before Reset DAC JESD core & SYSREF TRIGGER:

TX status after Reset DAC JESD core & SYSREF TRIGGER:

Alarm monitoring status:

Hi KAI,

1) All the "sysrefphase" related errors can be ignored because the SYSREF align block is bypassed in the default DAC configuration

2) "PLL in Rincewind1" related error is only relevant when using all 8 JESD lanes of DAC. There are 2 serdes PLLs in DAC. PLL0 is used for serdes lanes RX0 to RX3 and PLL1 is used for RX4 to RX7. If you are not using any of the RX4 to RX7 serdes inputs, then PLL1 will not be used.

From your waveform-hw_ila_2 screenshot, you are sending all zeros from the gtx transceivers. Can you fix this and transmit data to the DAC?

Thanks,
Eben.

Thanks for your supports Eben,
I fixed PLL in Rincewind1 error but I had another problem.
Following ug_HSDC Pro with Xilinx @ KCU105 document, i used DAC38RFxxEVM GUI to configure DAC and HSDC Pro GUI to configure and send data to FPGA. But I had a problem as below:
After data was sent from HSDC to FPGA (press send button) tx_reset_done signal of jesd204_phy = 1, tx_tdata = 0xbc.
And then, I press 'Reset DAC JESD core & SYSREF TRIGGER' on DAC GUI tx_reset_done signal of jed204_phy was always = 0. And data cannot be sent (tx_tdata = 0x00)

Waiting for your reply,
Thanks,
KAI

Thanks Eben,
I resolved this problem by CLKOUT12 enabled.
But I had a problem when I made simple project with JED204 and JESD204_PHY to connect with DAC38RF82. After core reset done, I saw 0xbcbc on tx_tdata but sync (from DAC JESD) was not upto 1 automatically.
Could you show me how to configura DAC to fix it?

Thanks,
KAI