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ADS42JB69: SYNC & SYSREF LVDS range

Mark Guastaferro
Genius 11645 points

Part Number: ADS42JB69
Other Parts Discussed in Thread: DS90LV001, LMK04828,

Quick question regarding the SYNC & SYSREF inputs to the ADS42JB69. 

The DS90LV001 LVDS buffer will be used to drive these signals from an FPGA, but we want to confirm the compatibility of the interface.  Here are the DS90’s LVDS driver specs:

 

 

Even though the AD42JB69 only gives a typical LVDS levels (Hi =1.3V, Lo = 0.5V, Vcm = 0.9V), I assume it can receive the DS90LV001 buffer's LVDS differential signal range. Is this correct?

The common mode voltages do not align: 1.19V for the DS90 and 0.9V for the ADS.  I assume this means the signals must be AC coupled. Please confirm.  

 

  • 0
    TI__Intellectual 2750 points
    Hello Mark,
    I did some reverse documentation from our EVM design:

    SYNCP/M each have a resistor network (182R to IOVDD3.3V) and (68R to GND) this gives a common mode bias of .9V
    - driven by the ArriaV FPGA (2.5V bank) pin Y7/AA7 (through FMC connector G12/G13)

    SYSREFP/M each have a resistor network (182R to IOVDD3.3V) and (68R to GND) this gives a common mode bias of .9V
    - driven by LMK04828 pins 13/14 (3.3V VCC)

    pin 13/14 LVDS CLOCK OUTPUTS (SDCLKoutY) Page 19 specifications of the LMK04828 look pretty close to your DS90LV buffer
    www.ti.com/.../lmk04828.pdf

    Based on this I think the DS90LV output matches what we have on our EVM from the LM04282. I do not think you should AC couple them.

    Regards,
    Brian
  • 0 in reply to Brian Kincaid
    TI__Mastermind 44680 points

    Hi Mark

    I would also recommend that SYSREF be generated by the same device that is sending the CLKP/M signals to the ADS42JB69. SYSREF must meet setup and hold timing with the CLK signal. At 250 MHz this is at most a 4ns window, and hitting that with an FPGA generated SYSREF may be difficult.

    That is why the LMK04828 is used to generate CLK and SYSREF on the ADS42JB69EVM.

    Best regards,

    Jim B

  • 0 in reply to Brian Kincaid
    TI__Genius 11645 points
    Hi Brian,
    I looked at the EVM interface, the termination scheme used here looks like what is used for a LVPECL signal. When looking at the EVM User Guide, it looks like the LMK04828 is set up to output LVPECL (2000mV) on the SYSREF signals, not LVDS. I don't know what signal type is coming out of the FPGA on the EVM for the SYNC signal, but I suspect its LVPECL as well.

    It seems this type of termination would have common mode mismatch problems for an LVDS signal source that is controlling the common mode voltage like the DS90LV001 device does. We also need to verify the LVDS signal swing is large enough for the ADS32JB69 receiver.
  • 0 in reply to Mark Guastaferro
    TI__Intellectual 2750 points
    Mark,
    I read up a bit more on the ADS42JB69. In the datasheet we have a section about driving the clocks (SYSREF is classified as a clock in the pin table)
    www.ti.com/.../ads42jb69.pdf
    Section 10.2.2.2 Clock Input has some diagrams and discussion about this configuration.

    I'm also checking the FPGA firmware to confirm its drive mode.

    Finally, I am going to have one of our engineers that has more experience on this device have a look as well.

    Regards,
    Brian
  • 0 in reply to Brian Kincaid
    TI__Intellectual 2750 points

    Hi Mark,

    I opened the TSW14J56 firmware project (it is on the TSW14J56EVM page if you are interested)

    The JESD_RX_SYNC pins (Y7/AA7) are set up as LVDS on a 2.5V bank.  

    Regards,

    Brian

  • 0 in reply to Brian Kincaid
    TI__Genius 11645 points

    Thanks, Brian,

    I'm gong to send you and Jim some additional information via email. 

  • 0 in reply to Mark Guastaferro
    TI__Intellectual 2750 points
    Mark,
    I think we took the thread offline. Can we move this status to resolved?
    Regards,
    Brian