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Linux/ADS1231: Question: Multiple chips for faster output.

FreddieTheRobot
Prodigy 40 points
Part Number: ADS1231
Other Parts Discussed in Thread: ADS1234, , ADS1232

Tool/software: Linux

Hello! 

So I have been doing a good bit of prototyping with the ADS123X line of ADCs, and was curious as to one thing.

As of right now, I have a 4-channel ADS1234 listening to 4 separate channels, talking to a raspberry pi. 
Everything is going perfectly; I have been bit banging the ADC to get data as quickly as possible and am getting fairly accurate results.
With my current python code I can get 70 samples per second happily on one channel. When I start swapping between channels, however, it seems that 'settling time' is bringing me down to about 20 samples happily, 5 on each channel per second. 

I would like to keep a high sample rate on each channel, so my next thought was to have four separate ADS1231's all reporting their own data. Would the following work?:

When I want to get data, I could have all four ADC's all tied to the same SCLK. As I apply SCLKs, the Raspberry Pi would shift in the data from each of the four channels, each with their respective DOUT pins tied to a different GPIO? That way I leave the organization of data between channels to the application, and the ADC can continue with high output rates, not worrying about any settling times.

Alternatively, is there a way that I could negate the settling time of the ADC1234, and therefore get a better sample rate? I'm not necessarily looking for 70 samples per second on each channel - but working at 5 samples per second on each definitely isn't going to work.

Thanks for your time!

  • 0
    TI__Guru** 113765 points
    Hi Freddie,

    Welcome to the E2E forum! There will be issues cycling through the mux of the ADS1234 due to the Sinc4 filter as you have discovered. The ADS1231 performance is not quite as good as the ADS1234, but it is pretty close. One thing that differs is the ADS1234 has a self offset calibration whereas the ADS1231 does not, so you will need to keep track of the offset in your code. You can certainly tie the single SCLK output from your controller to all four devices and read all four devices at the same time using 4 separate inputs.

    The biggest trick is keeping all four devices synchronized so that the conversions complete at the same time. You can use the PDWN pin to control the devices startup behavior, and should be able to resynchronize using the PDWN pin as well. Where there can be an issue is using the internal oscillators of the devices. In time, the devices will drift apart as to when the conversions complete and the data can be invalid if read out at the wrong time relative to the DOUT/DRDY transition from high to low. The best method of avoiding this is to use a single clock source to drive all 4 devices (CLKIN pin) either from your controller or from an external oscillator.

    Best regards,
    Bob B
  • 0 in reply to Bob Benjamin
    Prodigy 40 points
    Excellent! I just tried this with two 1234's on a single channel, works perfectly. Ordered 1231's, they are on the way!
    One more question, if I may:
    We are now moving into a new stage of development where I am testing outputs at a gain of 128 instead of unity gain.
    In the 1234 datasheet, it is specified that input operating voltage with a gain of 128 is AGND +1.5V to AVDD -1.5V in order to prevent "saturating the differential front end circuitry and degrading performance."
    So if I had a reference at AVDD = +5V and AGND = GND, is my best solution to offset my output by +2.5V? I'm not really sure if I'm thinking about this correctly, or why this is necessary.

    Will I have to worry about this with the ADS1231 chips? It says nothing about it in its respective datasheet, as the gain is always 128.

    Thanks again for your time!

    JM
  • 0 in reply to FreddieTheRobot
    TI__Guru** 113765 points
    Hi JM,

    If you use the ADS1232 at a gain of 128 (or the ADS1231 which is a fixed gain of 128) then the common-mode of the differential input to the ADC is limited to the specification you posted. It is generally a good target point to set the common-mode at mid-AVDD supply, or in your case 2.5V. The reason for the restriction is to prevent saturation of the PGA when attempts are made to drive the output close to the supply rails.

    One benefit of a load cell is that it is similar to a Wheatstone bridge. When the bridge is excited at 5V, then at the balanced (or no-load) condition the differential output is 0V, but the common-mode voltage is 2.5V (1/2 of the excitation). So in this case you are already at the correct operating voltages. Many other sensors work in a similar way. So depending on what type of sensor is connected you may not have to create a level shift into the proper common-mode range.

    Best regards,
    Bob B