ADC12DJ3200: ADC12DJ3200 Vih spec for CMOS Interface signals

I need to connect ADC12DJ3200 CMOS interface inputs/outputs to an FPGA bank powered from 1.8V, so I'm planning to use LVCMOS18 standard in FPGA logic. Looking at both FPGA (Xilinx document ds925, https://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf Table 14) and ADC specs so far I do not see any serious problems in doing so, but I'm wondering if the 0.7 V minimum spec for Vih on ADC12DJ3200 (table in chapter 6.3, Recommended Operating Conditions) is correct. Please confirm that 0.7V is the actual guaranteed minimum voltage for Vih signals.