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ADC08D1520: Is there a self generated clock in ADC08D1520?

Mark M.
Intellectual 255 points
Part Number: ADC08D1520


We have a test setup with the ADC08D1520 located on the main board and the ADC input clock source (CLK+/-) on a daughter board. In our testing we have found that when this ADC input clock source is removed, we can still successfully read the test pattern and our FPGA can lock on the ADC output clock. This seems to imply that the ADC is generating its own output clock.

Can the ADC08D1520 generate its own output clock? We could not find any mention of this capability in the data sheet. If it can generate its own output clock, what determines when it is on or off?

If it can't generate its own clock, should we expect to see a test pattern if the input clock pins are left floating?

Thanks.

  • 0
    TI__Mastermind 44680 points

    Hi Mark

    The ADC08D1520 differential clock receiver has a very high effective gain and doesn't have any hysteresis. Those characteristics combined with the AC-coupled nature of the CLK+/- connections from the clock source results in self-clocking from any thermal or coupled noise on the CLK+/- inputs. The frequency of operation isn't predictable, but it is expected that the ADC DCLK and DATA outputs will toggle when the AC-coupled clock is disabled.

    Since the frequency isn't predictable I would not rely on this behavior as a method to check the test pattern with the data receiver.

    The best way to prevent this is to place the ADC in power-down mode whenever the ADC clock source is disabled.

    Best regards,

    Jim B