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TSW1400EVM: tsw1400evm

Nikunj Agrawal
Prodigy 30 points
Part Number: TSW1400EVM


We are sending digital data (to tsw1400evm FPGA and tsw30sh84 DAC) and (using tsw1400evm and tsw1266evm to) finally capturing the digital data sent. We are using the same LO for both DAC and ADC. Will the internal clocks of DAC and ADC be synchronized or we need to do some other settings in the GUI?

  • 0
    TI__Guru* 91947 points

    Nikunj,

    I would suggest you synchronize both clock generator's. You have a couple of options for providing synchronization. The TSW1266EVM allows for multiple clocking configurations by using the LMK04800 clock jitter cleaner and generation chip. A 10-MHz reference can be applied to the CLKIN connector to synchronize the onboard clock with the signal sources. The TSW30SH84EVM can lock the on-board LMK VCO to the onboard 10MHz reference oscillator. This oscillator is also sent to an SMA which could then be used by the TSW1266EVM as a reference input on the OSCIN SMA connector.

    Another option is for both boards to use a common external source to feed the OSCIN input to lock their internal VCO's. This could be the 10MHz reference output from the LO signal generator used. 

     

    Both boards also have an option to run the LMK devices in clock distribution mode by providing an external clock to an SMA. In this case, you could route an external reference signal to a splitter and provide the outputs to both TSW boards.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 30 points
    Jim,

    We are using two tsw1400evm for dac and adc. We are running the LMK devices in single PLL mode and we are using the internal 10Mz reference (JP4 setting to 1-2) clock for TSW30SH84evm. We saw another thread regarding this question in which you suggested to connect J16 of tsw30sh84 to J8 of tsw1266. But in that you have mentioned that this will work for dual PLL mode. So can this also work in single PLL mode?
    If not, then in dual PLL mode, is it mandatory to give an external reference at J12?

    Is there some other way to synchronize two tsw1400evm connected to adc and dac if the internal clock is in single PLL mode and internal reference clock of 10Mz is used for dac?

    Regards,
    Nikunj
  • 0 in reply to Nikunj Agrawal
    TI__Guru* 91947 points
    Nikunj,

    If you can get two synchronized clocks and send one to J8 of the TSW1266EVM and the other to J12 of the TSW30SH84, this should work for single PLL mode. The higher this input frequency the lower the phase noise will be for the LMK outputs. The TSW1400 receives its clock source from the ADC and DAC EVM's so they should be synchronized.

    Regards,

    Jim