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ADS1282: ADS1283 Sync Issue

Kent Falkenstein
Prodigy 70 points
Part Number: ADS1282
Other Parts Discussed in Thread: ADS1283

Hi Chris,

We are using the ADS1282 in a single channel wireless seismic data acquisition system that is synchronized to GPS. Each data acquisition box has a GPS receiver and an ADS1282 and the ADS1282 is synchronized on the leading edge of the GPS 1 PPS signal after lock is achieved. We occasionally see timing errors in the data ranging from one sample to 16 samples or more. There is currently no provision to synchronize the SYNC signal to the CLK.

In a recent post on ADS1282 Synchronization, you indicated that the SYNC signal needed to stay at least 30ns away from the rising edge of the CLK. What range of errors would one be likely to see if the SYNC signal sometimes violates the CLK setup and hold timing?

You suggested toggling SYNC pin twice, (low-high-low-high). How fast or slow does this toggling have to be? For example, with SYNC initially low, would raising SYNC for 1us and then lowering it for 1us and then setting and leaving it high be sufficient?

- Kent

  • 0
    TI__Mastermind 44680 points

    Hi Kent,

    The issue with the SYNC pin timing is if the rising edge of SYNC corresponds to a rising CLK edge, that the SYNC command gets ignored. I believe this is the only error that occurs, and in all cases that I've seen, re-issuing the SYNC pulse usually resolves the problem.

    The datasheet of the ADS1283 provides more details of the SYNC pin timing requirements. This information also applies to the ADS1282.

     

    Kent Falkenstein said:
    You suggested toggling SYNC pin twice, (low-high-low-high). How fast or slow does this toggling have to be? For example, with SYNC initially low, would raising SYNC for 1us and then lowering it for 1us and then setting and leaving it high be sufficient?

    Yes, your example timing sequence should be fine as it satisfies the "tSPWH,L" timing requirement. However, this solution is just a workaround as there is still the possibility that both of the SYNC rising edges occur on CLK rising edges, but in practice it generally removes the problem.

    If you are only using the ADC's pulse-sync mode, then some better solutions would be to 1) route the SYNC pulse through a flip-flop to "re-clock" the SYNC pulse to the falling edge of the ADC CLK or 2) Use the SYNC SPI command instead of pulsing the SYNC pin, as the SPI command does not have this timing constraint with the ADC CLK.

     

    Best regards,
    Chris

  • 0 in reply to Christopher Hall
    Prodigy 70 points

    Thanks, that does clarify the issue.